In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic device structure comprising: an electronic device having first and second opposing major surfaces; a plurality of conductive pads on the first major surface; an insulative layer adjacent a portion of the second major surface; at least one conductive structure adjacent another portion of the second major surface and electrically coupled to the second major surface; a plurality of first conductive leads coupled to the insulative layer so that the electronic device overlaps the plurality of first conductive leads in a chip-on-lead configuration, where at least some of the plurality of first conductive leads are coupled to at least a portion of plurality of conductive pads; and a second conductive lead coupled to the at least one conductive structure.
2. The structure of claim 1 , where the plurality of first conductive leads and the second conductive lead substantially lie in the same plane.
3. The structure of claim 1 , where the second conductive lead is substantially perpendicular to the plurality of first conductive leads and extends from one edge of the electronic device to another edge opposite to the one edge.
4. The structure of claim 1 , where the second conductive lead includes a first portion having a first width and a second portion having a second width.
5. The structure of claim 4 , where the first width is greater than the second width, and where the first portion is coupled to the at least one conductive structure.
6. The structure of claim 1 , where one of the insulative layer and the at least one conductive structure comprises an epoxy.
7. The structure of claim 1 , where the electronic device comprises a semiconductor device, and wherein the second major surface is devoid of individual doped regions.
8. The structure of claim 7 further comprising a conductive layer between the second major surface and the insulative layer.
9. The structure of claim 1 further comprising an encapsulating layer covering the electronic device structure, where portions of the plurality of first conductive leads and a portion of the second conductive lead are exposed through the encapsulating layer.
10. The structure of claim 1 , where the at least one conductive structure is located in a substantially centrally portion of the second major surface.
11. An electronic device structure comprising: a first conductive lead; a second conductive lead; and an electronic device having first and second opposing major surfaces, wherein the electronic device overlaps the first and second leads in a chip-on-lead configuration, and wherein the second major surface is electrically coupled to the second conductive lead, and wherein the second major surface is electrically isolated from the first conductive lead.
12. The structure of claim 11 further comprising a conductive pad overlying the first major surface, wherein the conductive pad is electrically coupled to the first conductive lead.
13. The structure of claim 11 , wherein the second major surface is electrically coupled to the second conductive lead with a conductive epoxy material.
14. The structure of claim 11 , wherein the second major surface is electrically isolated from the first conductive lead with a non-conductive epoxy material.
15. The structure of claim 11 further comprising an encapsulating material over at least portions of the first and second conductive leads and the electronic device.
16. An electronic package comprising: a plurality of first conductive leads and a second conductive lead; an insulative layer overlying at least a portion of the plurality of first conductive leads; at least one conductive structure overlying a portion of the second conductive lead; and an electronic device having first and second opposing major surfaces, wherein the second opposing major surface is overlying the insulative layer and a portion of the plurality of first conductive leads so that the electronic device overlaps the plurality of first conductive leads, and wherein the second opposing major surface is overlying the at least one conductive structure and a portion of the second conductive lead, and wherein the second opposing surface is electrically coupled to the second conductive lead by the at least one conductive structure.
17. The electronic package of claim 16 further comprising: a plurality of connective structures electrically coupled to the first opposing major surface and to at least some of the plurality of first conductive leads.
18. The electronic package of claim 16 , where the plurality of first conductive leads and the second conductive lead substantially lie in the same plane, such that the electronic package is devoid of an electronic device pad.
19. The electronic package of claim 16 , wherein the second conductive lead provides for independent electrical biasing of the second opposing major surface of the electronic device.
20. The electronic package of claim 16 , wherein the insulative layer also overlies a portion of the second conductive lead.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 20, 2012
June 24, 2014
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