Amplifier architectures are provided for current sensing applications. An amplifier includes a load device, an operational amplifier, a current source, and a bipolar transistor. The operational amplifier has a first input terminal connected to a first input node that receives an input current, and a second input terminal connected to a second input node that receives a reference voltage. The current source is connected to an output of the operational amplifier. The operational amplifier, the current source, and the bipolar transistor form a feedback loop that generates and maintains a bias voltage on the first input node based on the reference voltage applied to the second input node. The bipolar transistor amplifies the input current received on the first input node, and generates an amplified input current. The load device converts the amplified input current to an output voltage, wherein the output voltage is used to sense the input current.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An amplifier circuit, comprising; a first input node to receive an input current, a second input node to receive an input reference voltage, and an output node; a first supply voltage node and a second supply voltage node; a load device connected between the output node and the first supply voltage node; an operational amplifier having a first input terminal connected to the first input node, a second input terminal connected to the second input node, and an output terminal; a current source connected to the output terminal of the operational amplifier and to the second supply voltage node; and a bipolar transistor having a base terminal connected to the first input node, a collector terminal connected to the output node, and an emitter terminal connected to the current source, wherein the operational amplifier, the current source, and the bipolar transistor form a feedback loop that generates and maintains a bias voltage on the first input node based on the input reference voltage applied to the second input node, wherein the bipolar transistor amplifies the input current that is input to the base terminal and generates a collector current as the amplified input current, and wherein the load device converts the collector current of the bipolar transistor to an output voltage on the output node.
2. The amplifier circuit of claim 1 , wherein the load device comprises a diode-connected field effect transistor.
3. The amplifier circuit of claim 1 , wherein the load device comprises a resistor.
4. The amplifier circuit of claim 1 , wherein the current source comprises a field effect transistor having a gate terminal connected to the output terminal of the operational amplifier.
5. The amplifier circuit of claim 1 , further comprising a resistor connected between the emitter terminal of the bipolar transistor and the current source.
6. The amplifier circuit of claim 1 , further comprising a programmable reference voltage source connected to the second input node of the amplifier circuit to generate the input reference voltage.
7. The amplifier circuit of claim 1 , further comprising a sensor element connected to the first input node of the amplifier circuit to generate a sensor current which is input to the base terminal of the bipolar transistor.
8. The amplifier circuit of claim 7 , wherein the sensor element is an element on a read/write head of a storage device.
9. The amplifier circuit of claim 1 , further comprising a comparing circuit connected to the output node of the amplifier circuit, wherein the comparing circuit compares the output voltage with an output reference voltage to detect when the input current is at a predetermined level.
10. The amplifier circuit of claim 1 , wherein the amplifier circuit is fabricated as part of an integrated circuit.
11. An amplifier circuit, comprising: a first input node to receive an input current, a second input node to receive a reference voltage, and an output node; a first supply voltage node and a second supply voltage node; a first amplifier circuit comprising: an operational amplifier having a first input terminal connected to the first input node, a second input terminal connected to the second input node, and an output terminal; a first current source connected to the output terminal of the operational amplifier and to the second supply voltage node; and a first bipolar transistor having a base terminal connected to the first input node, a collector terminal connected to the first supply voltage node, and an emitter terminal connected to the first current source; and a second amplifier circuit comprising: a second current source connected to the output terminal of the operational amplifier and to the second supply voltage node; a second bipolar transistor having a base terminal, a collector terminal connected to the first supply voltage node, and an emitter terminal connected to the first current source; and a current mirror circuit connected to the base terminal of the second bipolar transistor, the first supply voltage node, and the output node.
12. The amplifier circuit of claim 11 , wherein the operational amplifier, the first current source, and the first bipolar transistor form a feedback loop that generates and maintains a bias voltage on the first input node based on the reference voltage applied to the second input node.
13. The amplifier circuit of claim 11 , wherein the first and second current sources are first and second field effect transistors that are matched and scaled by M, wherein the operational amplifier outputs a control voltage to drive gate terminals of the first and second field effect transistors to generate a first emitter current that flows from the first bipolar transistor and generate a second emitter current that flows from the second bipolar transistor, wherein the second emitter current is an M-scaled version of the first emitter current.
14. The amplifier circuit of claim 13 , wherein the second bipolar transistor generates a base current which is an M-scaled version of an input current at the base terminal of the first bipolar transistor, and wherein the current mirror generates a K-scaled version of the base current of the second bipolar transistor and outputs an output current from the output node of the amplifier circuit, wherein the output current is a K*M scaled version of the input current at the base terminal of the first bipolar transistor.
15. The amplifier circuit of claim 14 , further comprising a current comparing circuit connected to the output node of the amplifier circuit, wherein the current comparing circuit compares the output current with a reference current to detect when the input current at the base terminal of the first bipolar transistor is at a predetermined level.
16. The amplifier circuit of claim 11 , further comprising a sensor element connected to the first input node of the amplifier circuit to generate a sensor current which is input to the base terminal of the first bipolar transistor.
17. The amplifier circuit of claim 16 , wherein the sensor element is an element on a read/write head of a storage device.
18. The amplifier circuit of claim 11 , further comprising: a first resistor connected between the emitter terminal of the first bipolar transistor and the first current source; and a second resistor connected between the emitter terminal of the second bipolar transistor and the second current source.
19. The amplifier circuit of claim 11 , further comprising a programmable reference voltage source connected to the second input node of the amplifier circuit to generate the reference voltage.
20. The amplifier circuit of claim 11 , wherein the amplifier circuit is fabricated as part of an integrated circuit.
21. A storage system, comprising: a storage medium; a read/write head to read and write data to and from the storage medium, wherein the read/write head comprises a sensor element to generate a sensor current as the read/write head approaches a surface of the storage medium; and current sensor circuitry to process the sensor current generated by the sensor element to detect when the read/write head is positioned at a predefined distance from the surface of the storage medium based on a predetermined level of the sensor current, wherein the current sensor circuitry comprises: an amplifier circuit, comprising: a first input node to receive the sensor current, a second input node to receive an input reference voltage, and a first output node; a first supply voltage node and a second supply voltage node; a first load device connected between the first output node and the first supply voltage node; a first operational amplifier having a first input terminal connected to the first input node, a second input terminal connected to the second input node, and an output terminal; a first current source connected to an output terminal of the first operational amplifier and to the second supply voltage node; and a first bipolar transistor having a base terminal connected to the first input node, a collector terminal connected to the first output node, and an emitter terminal connected to the first current source, wherein the first operational amplifier, the first current source, and the first bipolar transistor form a feedback loop that generates and maintains a bias voltage on the first input node based on the input reference voltage applied to the second input node, wherein the first bipolar transistor amplifies the sensor current that is input to the base terminal of the first bipolar transistor and generates a collector current as the amplified sensor current, and wherein the first load device converts the collector current of the first bipolar transistor to an output voltage on the first output node; and a voltage comparing circuit connected to the first output node of the amplifier circuit, wherein the voltage comparing circuit compares the output voltage with an output reference voltage to detect when the sensor current is at the predetermined level, wherein the voltage comparing circuit generates a control signal when the sensor current is detected to be at the predetermined level.
22. The storage system of claim 21 , further comprising a reference circuit to generate the output reference voltage, wherein the amplifier circuit and the reference circuit have one or more matching components that are scaled by a factor of M such that the output voltage and output reference voltage are a function of a device size ratio of matching components in the amplifier circuit and the reference circuit.
23. The storage system of claim 22 , wherein the reference circuit comprises: a reference node; a second output node; a second operational amplifier matched to the first operational amplifier; a second current source matched to the first current source; a second bipolar transistor matched to the first bipolar transistor; a second load device matched to the first load device, and a reference current source that generates a reference current to the reference node.
24. The storage system of claim 23 , wherein the second bipolar transistor has a base terminal connected to the reference node to receive the reference current output from the reference current source, a collector terminal connected to the second output node, and an emitter terminal, wherein the second load device is connected between the second output node and the first voltage supply node; wherein the second current source is connected between the emitter terminal of the second bipolar transistor and the second voltage supply node; wherein the second operational amplifier has a first input terminal connected to the reference node, a second input terminal connected to the second input node, and an output terminal connected to the second current source; wherein the second operational amplifier, the second current source, and the second bipolar transistor form a feedback loop that generates and maintains a same bias voltage on the reference node, which is on the first input node, based on the reference voltage applied to the second input node, wherein the second bipolar transistor amplifies the reference current that is input to the base terminal of the second bipolar transistor to generate a collector current as the amplified reference current, and wherein the second load device converts the collector current of the second bipolar transistor to an output reference voltage on the second output node.
25. The storage system of claim 24 , wherein the first and second load devices are matched diode-connected field effect transistor devices that are scaled at a 1:M ratio.
26. The storage system of claim 24 , wherein the first and second load devices are resistors having respective resistance values that are scaled at a 1:1/M ratio.
27. The storage system of claim 24 , wherein the reference current is a M-scaled version of the predetermined level of the sensor current.
28. The storage system of claim 24 , further comprising a first resistor connected between the emitter terminal of the first bipolar transistor and the first current source, and a second resistor connected between the emitter terminal of the second bipolar transistor and the second current source.
29. A virtual storage system comprising the storage system of claim 21 .
30. A storage system, comprising: a storage medium; a read/write head to read and write data to and from the storage medium, wherein the read/write head comprises a sensor element to generate a sensor current as the read/write head approaches a surface of the storage medium; and current sensor circuitry to process the sensor current generated by the sensor element to detect when the read/write head is positioned at a predefined distance from the surface of the storage medium based on a predetermined level of the sensor current, wherein the current sensor circuitry comprises: an amplifier circuit, comprising: a first input node to receive the sensor current, a second input node to receive a reference voltage, and an output node; a first supply voltage node and a second supply voltage node; a first amplifier circuit; and a second amplifier circuit, wherein the first amplifier circuit comprises: an operational amplifier having a first input terminal connected to the first input node, a second input terminal connected to the second input node, and an output terminal; a first current source connected to the output terminal of the operational amplifier and to the second supply voltage node; and a first bipolar transistor having a base terminal connected to the first input node, a collector terminal connected to the first supply voltage node, and an emitter terminal connected to the first current source; and wherein the second amplifier circuit comprises: a second current source connected to the output terminal of the operational amplifier and to the second supply voltage node; a second bipolar transistor having a base terminal, a collector terminal connected to the first supply voltage node, and an emitter terminal connected to the first current source; and a current mirror circuit connected to the base terminal of the second bipolar transistor, the first supply voltage node, and the output node; and a current comparing circuit connected to the output node of the amplifier circuit, wherein the current comparing circuit compares a current output from the output node of the amplifier circuit with a reference current to detect when the sensor current is at the predetermined level, wherein the current comparing circuit generates a control signal when the sensor current is detected to be at the predetermined level.
31. The storage system of claim 30 , wherein the operational amplifier, the first current source, and the first bipolar transistor form a feedback loop that generates and maintains a bias voltage on the first input node based on the reference voltage applied to the second input node.
32. The storage system of claim 30 , wherein the first and second current sources are first and second field effect transistors that are matched and scaled by M, wherein the operational amplifier outputs a control voltage to drive gate terminals of the first and second field effect transistors to generate a first emitter current that flows from the first bipolar transistor and generate a second emitter current that flows from the second bipolar transistor, wherein the second emitter current is an M-scaled version of the first emitter current.
33. The storage system of claim 32 , wherein the second bipolar transistor generates a base current which is an M-scaled version of the sensor current at the base terminal of the first bipolar transistor, and wherein the current mirror generates a K-scaled version of the base current of the second bipolar transistor and outputs an output current from the output node of the amplifier circuit, wherein the output current is a K*M scaled version of the sensor current input to the base terminal of the first bipolar transistor.
34. A virtual storage system comprising the storage system of claim 30 .
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November 12, 2012
June 24, 2014
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