A complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with no well contacts within the memory array. Modern sub-micron CMOS structures have been observed to have reduced vulnerability to latchup. Chip area is reduced by providing no well contacts within the array. Wells of either or both conductivity types may electrically float during operation of the memory. In other implementations, extensions of the array wells into peripheral circuitry may be provided, with well contacts provided in those extended portions.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A solid-state memory in an integrated circuit formed at a semiconducting surface of a body, the memory comprising: a plurality of memory cells arranged in rows and columns within a generally rectangular bit array area of the semiconducting surface, each memory cell including two or more transistors, each having a channel region disposed in a first well region of the semiconducting surface doped to a first conductivity type; one or more bias conductors for applying a bias voltage routed within the bit array area, each physically contacting a doped region in one or more of the memory cells; one or more signal conductors routed within the bit array area, each physically contacting a doped region in one or more of the memory cells; and peripheral circuitry disposed in a peripheral area adjacent to the bit array area and coupled to the one or more signal conductors; wherein, within the bit array area, doped regions only of a second conductivity type, opposite the first conductivity type, are disposed within the first well region and are physically contacted by one of the bias conductors.
2. The memory of claim 1 , wherein the first well region has a portion extending beyond the bit array area into the peripheral area; and further comprising: a doped region of the first conductivity type formed into the first well region at its portion extending into the peripheral area and physically contacted by one of the bias conductors.
3. The memory of claim 1 , wherein the first well region has a portion extending beyond the bit array area into the peripheral area; and further comprising: one or more periphery bias conductors for applying bias voltage, routed within the peripheral area and physically contacting one or more doped regions in the periphery circuitry; and a doped region of the first conductivity type formed into the first well region at its portion extending into the peripheral area and physically contacted by one of the periphery bias conductors.
4. The memory of claim 1 , wherein the first well region includes no doped region of the first conductivity type that is physically contacted by one of the bias conductors.
5. The memory of claim 4 , wherein, during operation of the memory, the first well region is electrically floating.
6. The memory of claim 1 , wherein each memory cell further includes two or more transistors, each having a channel region disposed in a second well region of the semiconducting surface doped to the second conductivity type; and wherein within the bit array area, doped regions only of the first conductivity type are disposed within the second well region and are physically contacted by one of the bias conductors.
7. The memory of claim 6 , wherein the second well region has a portion extending beyond the bit array area into the peripheral area; and further comprising: a doped region of the second conductivity type formed into the second well region at its portion extending into the peripheral area and physically contacted by one of the bias conductors.
8. The memory of claim 6 , wherein the second well region has a portion extending beyond the bit array area into the peripheral area; and further comprising: one or more periphery bias conductors for applying bias voltage, routed within the peripheral area and physically contacting one or more doped regions in the periphery circuitry; and a doped region of the second conductivity type formed into the second well region at its portion extending into the peripheral area and physically contacted by one of the periphery bias conductors.
9. The memory of claim 6 , wherein the second well region includes no doped region of the second conductivity type that is physically contacted by one of the bias conductors, whereby, during operation of the memory, the second well region is electrically floating.
10. The memory of claim 6 , wherein the first well region includes no doped region of the first conductivity type that is physically contacted by one of the bias conductors, whereby, during operation of the memory, the second well region is electrically floating; and further comprising: a deep well region of the second conductivity type, in contact with the second well region, and underlying the first well region.
11. The memory of claim 1 , wherein the first well region includes two or more transistors of a column of memory cells; and further comprising: a plurality of well regions of the first conductivity type, each including two or more transistors of a column of memory cells.
12. The memory of claim 11 , wherein each of a plurality of the memory cells comprises: first and second cross-coupled inverters, each comprising a p-channel field-effect transistor and an n-channel field effect transistor, the p-channel transistors each having a channel region disposed in one of the well regions of the first conductivity type, each inverter having an output, and each inverter having an input coupled to the output of the other inverter; and first and second pass transistors, each having a source/drain path coupled between an output of a corresponding one of the first and second inverters and a bit line for the column, and having a gate electrode coupled to a word line.
13. The memory of claim 11 , wherein each of the memory cells comprises: first and second cross-coupled inverters, each comprising a p-channel field-effect transistor and an n-channel field-effect transistor, the p-channel transistors each having a channel region disposed in one of the well regions of the first conductivity type, each inverter having an output, and each inverter having an input coupled to the output of the other inverter; and first and second pass transistors, each having a source/drain path coupled between an output of a corresponding one of the first and second inverters and a write bit line for the column including the memory cell, and having a gate electrode coupled to a write word line for the row including the memory cell; a buffer circuit disposed within the bit cell area nearer to the first inverter than to the second inverter, and comprising: a first buffer transistor having a source/drain path, and having a gate connected to a read word line for the row including the memory cell; and a second buffer transistor having a source/drain path in series with the source/drain path of the first buffer transistor between a read bit line for the column including the memory cell and a reference voltage, and having a gate connected to the output of the second inverter.
14. The memory of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.
15. The memory of claim 14 , wherein the body comprises a p-type substrate.
16. A method of operating a solid-state memory in an integrated circuit formed at a semiconducting surface of a body, wherein the memory comprises a plurality of memory cells arranged in rows and columns within a generally rectangular bit array area of the semiconducting surface, each memory cell comprising first and second cross-coupled inverters and a first pass transistor, each column of memory cells associated with a first bit line coupled to the first pass transistor of the memory cells in the column, each row of memory cells associated with a word line coupled to gates of the pass transistors of the memory cells in the row; wherein each memory cell including two or more transistors, each having a channel region disposed in a first well region of the semiconducting surface doped to a first conductivity type; the method comprising: applying a bias voltage to the first and second inverters of a selected memory cell while electrically floating the first well region; during the applying step, energizing the word line for the row including the selected memory cell; and during the applying step, sensing the state of the bit line of the column including the selected memory cell.
17. The method of claim 16 , further comprising: during the applying step, writing a first data state to the selected memory cell.
18. The method of claim 16 , wherein each memory cell further includes two or more MOS transistors, each having a channel region disposed in a second well region of the semiconducting surface doped to a second conductivity type opposite the first conductivity type; wherein the applying step further comprises applying the bias voltage to the first and second inverters of the selected memory cell while electrically floating the second well region.
19. A method of fabricating a memory in an integrated circuit, comprising the steps of: forming a first well region of a first conductivity type at a semiconducting surface of a body; forming gate electrodes in each of a plurality of adjacent bit cell areas in a bit array area of the semiconducting surface, including at locations overlying the first well region; forming doped regions of a second conductivity type, opposite the first conductivity type, on opposite sides of at least two gate electrodes in the first well region in each bit cell area, to define first and second transistors in a memory cell; forming doped regions of the first conductivity type on opposite sides of gate electrodes outside of the first well region in each bit cell area, to define one or more additional transistors within each of the bit cell areas; forming interconnections among the doped regions and gate electrodes of the first and second transistors and additional transistors within each bit cell area to define first and second cross-coupled inverters, the first inverter including the first transistor and the second inverter including the second transistor; and forming bias conductors physically contacting one or more doped regions in the bit cell area; wherein, within the bit array area, doped regions only of the second conductivity type are disposed within the first well region and are physically contacted by one of the bias conductors.
20. The method of claim 19 , wherein the step of forming the first well region forms the first well region to have a portion outside of the bit array area, and extending into a peripheral circuit area of the semiconducting surface; wherein the step of forming doped regions of the first conductivity type also forms at least one doped region of the first conductivity type at the portion of the first well region in the peripheral circuit area; and wherein the step of forming bias conductors forms at least one bias conductor physically contacting the at least one doped region of the first conductivity type at the portion of the first well region in the peripheral circuit area.
21. The method of claim 19 , wherein the step of forming the first well region forms the first well region to have a portion outside of the bit array area, and extending into a peripheral circuit area of the semiconducting surface; wherein the step of forming doped regions of the first conductivity type also forms at least one doped region of the first conductivity type at the portion of the first well region in the peripheral circuit area; and further comprising: forming one or more peripheral bias conductors physically contacting one or more doped regions in the peripheral circuit area, and contacting the at least one doped region of the first conductivity type at the portion of the first well region in the peripheral circuit area.
22. The method of claim 19 , further comprising: forming a second well region of a second conductivity type at the semiconducting surface and within the bit array area; wherein the step of forming doped regions of the first conductivity type forms those doped regions within the second well region; and wherein, within the bit array area, only doped regions of the first conductivity type are disposed within the second well region and are physically contacted by one of the bias conductors.
23. The method of claim 22 , wherein the step of forming the second well region forms the second well region to have a portion outside of the bit array area, and extending into the peripheral circuit area; wherein the step of forming doped regions of the second conductivity type also forms at least one doped region of the second conductivity type at the portion of the second well region in the peripheral circuit area; and wherein the step of forming bias conductors forms at least one bias conductor physically contacting the at least one doped region of the second conductivity type at the portion of the second well region in the peripheral circuit area.
24. The method of claim 22 , wherein the step of forming the first well region forms the first well region to have a portion outside of the bit array area, and extending into a peripheral circuit area of the semiconducting surface; wherein the step of forming doped regions of the second conductivity type also forms at least one doped region of the second conductivity type at the portion of the second well region in the peripheral circuit area; and further comprising: forming one or more peripheral bias conductors physically contacting one or more doped regions in the peripheral circuit area, and contacting the at least one doped region of the second conductivity type at the portion of the second well region in the peripheral circuit area.
25. The method of claim 22 , wherein the semiconducting surface is of the first conductivity type; and further comprising: forming a deep well region of the second conductivity type at a location of the bit array area underlying the location of the first well region; wherein the step of forming the second well region forms the second well region to a depth that contacts the deep well region.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 25, 2012
June 24, 2014
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