Patentable/Patents/US-8765579
US-8765579

Semiconductor wafer processing method

PublishedJuly 1, 2014
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A semiconductor wafer has a device area where a plurality of semiconductor devices are respectively formed in a plurality of regions partitioned by a plurality of crossing division lines formed on the front side of the semiconductor wafer and a peripheral area surrounding the device area. The back side of the semiconductor wafer corresponding to the device area is ground to thereby form a circular recess and an annular projection surrounding the circular recess. In a chip stacked wafer forming step, a plurality of semiconductor device chips are provided on the bottom surface of the circular recess of the semiconductor wafer at the positions respectively corresponding to the semiconductor devices of the semiconductor wafer. The chip stacked wafer is ground to reduce the thickness of each semiconductor device chip to a finished thickness, and a through electrode is formed in each semiconductor device of the semiconductor wafer.

Patent Claims
2 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A processing method for a semiconductor wafer having a device area where a plurality of semiconductor devices are respectively formed in a plurality of regions partitioned by a plurality of crossing division lines formed on a front side of said semiconductor wafer and a peripheral marginal area surrounding said device area, said processing method comprising: a protective tape attaching step of attaching a protective tape to the front side of said semiconductor wafer; a grinding step of grinding the back side of said semiconductor wafer in a central area corresponding to said device area to thereby form a circular recess and an annular projection surrounding said circular recess after performing said protective tape attaching step; a chip stacked wafer forming step of providing a plurality of semiconductor device chips on a bottom surface of said circular recess of said semiconductor wafer at the positions respectively corresponding to said semiconductor devices of said semiconductor wafer in a condition where the device surface of each semiconductor device chip comes into contact with the bottom surface of said circular recess and filling a filler into said circular recess until reaching a depth corresponding to a finished thickness of each semiconductor device chip to thereby form a chip stacked wafer after performing said grinding step; a thickness reducing step of grinding the back side of said chip stacked wafer to thereby reduce the thickness of each semiconductor device chip to said finished thickness after performing said chip stacked wafer forming step; and a through electrode forming step of forming a through electrode in each semiconductor device of said semiconductor wafer after performing said thickness reducing step.

2

2. The processing method for a semiconductor wafer according to claim 1 , further comprising a dividing step of dividing said chip stacked wafer along said division lines after performing said through electrode forming step.

Classification Codes (CPC)

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Patent Metadata

Filing Date

June 20, 2012

Publication Date

July 1, 2014

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Cite as: Patentable. “Semiconductor wafer processing method” (US-8765579). https://patentable.app/patents/US-8765579

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