Patentable/Patents/US-8769207
US-8769207

Caching method and apparatus for a vertex shader and geometry shader

PublishedJuly 1, 2014
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

Systems and methods for sharing a physical cache among one or more clients in a stream data processing pipeline are described. One embodiment is directed to a system for sharing caches between two or more clients. The system comprises a physical cache memory having a memory portion accessed through a cache index. The system further comprises at least two virtual cache spaces mapping to the memory portion, each of the virtual cache spaces has an active window which has a different size than the memory portion. Further, the system comprises at least one virtual cache controller configured to perform a hit-miss test on the active window of the virtual cache space in response to a request from one of the clients for accessing the physical cache memory. Furthermore, data is accessed from the corresponding location of the memory portion when the hit-miss test of the cache index returns a hit.

Patent Claims
19 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A system for sharing caches between two or more clients in a stream data processing pipeline, the system comprising: a physical cache memory having a memory portion accessed through a cache index; a virtual cache space comprising N entries, the N entries comprising a continuous portion of M entries, the continuous portion mapped to the memory portion, where M and N are integer numbers and M is less than N, and the mapped continuous portion is shifted incrementally based on allocation of an entry to the virtual cache space; a vertex index space comprising M virtual valid tag entries, the M virtual valid tag entries mapped to the M entries of the continuous portion; and a virtual cache controller configured to provide the cache index for use by one of the clients based on performing a hit-miss test on the continuous portion in response to a vertex index received at the vertex index space.

2

2. The system as recited in claim 1 , wherein the virtual cache controller allocates a new entry within the virtual cache space if the hit-miss test returns a miss.

3

3. The system as recited in claim 1 , wherein the physical cache memory further comprises a status table including: a valid bit indicating whether the data associated with the cache index has completed execution; and an in-cache bit indicating whether the data associated with the cache index is present in the physical cache memory.

4

4. The system as recited in claim 1 , wherein the continuous portion is smaller than the memory portion and is managed by a pair of pointers indicating the current valid entries.

5

5. The system as recited in claim 4 , wherein the virtual cache space further comprises a third pointer configured to point to the next entry to be invalidated.

6

6. The system as recited in claim 1 , wherein each entry of the virtual cache space comprises information bits configured to indicate an accessing status of data associated with the entry.

7

7. The system as recited in claim 1 , wherein the one of the clients comprises a vertex shader and another of the clients comprises a geometry shader.

8

8. The system as recited in claim 1 , wherein the virtual cache controller performs the hit-miss test by matching the cache index with every entry within the continuous portion.

9

9. A method for accessing a physical cache by two or more clients, the method comprising: mapping M virtual valid tag entries of a vertex index space to M entries of a continuous portion of a virtual cache space, the virtual cache space comprising N entries, the N entries comprising a subset of the M entries that correspond to the continuous portion, where M and N are integer numbers and M is less than N; mapping the continuous portion to a memory portion of the physical cache; receiving at the vertex index space a vertex index; performing by a virtual cache controller a hit-miss test on the continuous portion based on the vertex index; providing by the virtual cache controller a cache index based on the hit-miss test; and shifting incrementally the mapped continuous portion based on allocation of an entry to the virtual cache space.

10

10. The method as recited in claim 9 , wherein providing comprises allocating a new entry in the virtual cache space if the hit-miss test returns a miss.

11

11. The method as recited in claim 9 , wherein performing comprises comparing the vertex index to an invalidation pointer configured to point to the next entry to be invalidated in the virtual cache space.

12

12. The method as recited in claim 9 further comprising updating status bits of the entry of the virtual cache space.

13

13. The method as recited in claim 9 , wherein the mapping further comprises mapping each entry of the memory portion to a status table, the status table including information of data validation and presence of the entry.

14

14. A graphic processing system, comprising: a physical cache having a plurality of slots for storing data; and a cache controller configured to allocate memory space within the physical cache, wherein the memory space is determined by a set of pointers that define a continuous portion of M entries in virtual cache space, the virtual cache space comprising N entries that include the M entries, where M and N are integer numbers and M is less than N, the M entries of the continuous portion mapped from M virtual valid tag entries in a vertex index space, the continuous portion subject to a hit-miss test, wherein the mapped continuous portion is shifted incrementally based on allocation of an entry to the virtual cache space.

15

15. The graphics processing system as recited in claim 14 , further comprising a status table that contains a current pointer and an in-cache indicator, wherein the in-cache indicator indicates whether data to be accessed is already present within the physical cache, and wherein the status table is used to track a distance of each slot of the physical cache.

16

16. The graphics processing system as recited in claim 15 , wherein the slot with the greatest distance from being read is removed and written to an L2 cache or other memory device prior to other valid entries.

17

17. The graphics processing system as recited in claim 15 , wherein the distance is calculated by calculating the difference between a current invalidation pointer and the current pointer, wherein the invalidation pointer specifies a read location for the next pipeline stage for each of the clients.

18

18. The graphics processing system as recited in claim 14 , wherein the physical cache is shared by pipeline stages within the graphics processing system, and wherein the plurality of clients have different cache access patterns.

19

19. The graphics processing system as recited in claim 14 , wherein the plurality of clients comprises a vertex shader and a geometry shader.

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Patent Metadata

Filing Date

January 16, 2008

Publication Date

July 1, 2014

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Cite as: Patentable. “Caching method and apparatus for a vertex shader and geometry shader” (US-8769207). https://patentable.app/patents/US-8769207

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