One illustrative method disclosed herein involves forming an etch stop layer above a plurality of sacrificial gate structures, performing an angled ion implant process to implant an etch-inhibiting species into less than an entirety of the etch stop layer, and forming a layer of insulating material above the etch stop layer. The method further includes removing the sacrificial gate structures, forming replacement gate structures, forming a hard mask layer above the replacement gate structures and layer of insulating material, forming a patterned hard mask layer, performing another etching process through the patterned hard mask layer to define an opening in the layer of insulating material to expose a portion of the etch stop layer, performing another etching process on the exposed portion to define a contact opening therethrough that exposes a doped region and forming a conductive contact in the opening that is conductively coupled to the doped region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method, comprising: forming sacrificial gate structures for first and second spaced-apart transistors above a semiconducting substrate; forming an etch stop layer above said substrate and said sacrificial gate structures for said transistors; performing at least one angled ion implant process to implant at least one etch-inhibiting species into less than an entirety of said etch stop layer; after performing said at least one angled ion implant process, forming a layer of insulating material above said etch stop layer; performing at least one chemical mechanical polishing process to expose at least a portion of each of said sacrificial gate structures; performing at least one first etching process to remove said sacrificial gate structures and thereby define a plurality of gate cavities; forming a replacement gate structure in each of said cavities; forming a hard mask layer above said replacement gate structures and said layer of insulating material; performing a second etching process on said hard mask layer to define a patterned hard mask layer, wherein an entire upper surface of said hard mask layer is exposed to said second etching process; performing at least one third etching process through said patterned hard mask layer to define an opening in said layer of insulating material and thereby expose a portion of said etch stop layer; performing a fourth etching process on said exposed portion of said etch stop layer to define a contact opening therethrough that exposes a doped region formed in said substrate; and forming a conductive contact in said opening that is conductively coupled to said doped region.
2. The method of claim 1 , wherein performing said fourth etching comprises performing a wet etching process or a dry, plasma-based etching process.
3. The method of claim 1 , wherein said etch-inhibiting species is a polymer-forming species and wherein performing said fourth etching process comprises performing a dry plasma-based etching process that causes formation of a polymer material proximate where said polymer-forming species have been implanted into said etch stop layer.
4. The method of claim 1 , wherein performing said fourth etching process on said etch stop layer comprises performing a carbon-fluorine based plasma etching process on said etch stop layer.
5. The method of claim 1 , wherein performing said fourth etching process comprises performing a plasma etching process using at least one of the following process gases: C 4 F 8 /CH 2 F 2 /Ar, C 4 F 6 /CO/Ar, C 4 F 6 , or C 5 F 8 and nitrogen.
6. The method of claim 1 , wherein performing said fourth etching process comprises performing a wet etching process that causes formation of a protective interfacial layer proximate where said at least one etch-inhibiting species have been implanted into said etch stop layer.
7. The method of claim 1 , wherein said at least one angled implant process is performed at an angle such that said first transistor prevents the implantation of said at least one etch-inhibiting species into the entirety of the etch stop layer positioned proximate a side of said second transistor.
8. The method of claim 1 , wherein said at least one angled implant process is performed at an angle such that a portion of said etch stop layer between said first and second transistors is not implanted with said etch-inhibiting species.
9. The method of claim 1 , wherein said at least one angled implant process is performed at an angle such that portions of said etch stop layer within a vertical distance above a surface of said substrate that corresponds to approximately 30% of a gate height of one of said sacrificial gate structures is not implanted with said etch-inhibiting species.
10. The method of claim 9 , wherein said vertical distance is about 40 nm or less.
11. The method of claim 1 , wherein said at least one angled implant process is performed at an angle such that only portions of said etch stop layer that are positioned a vertical distance above a surface of said substrate that is greater than a distance that corresponds to approximately 30% of a gate height of one of said sacrificial gate structures is implanted with said etch-inhibiting species.
12. The method of claim 1 , wherein said angled ion implant process is performed at an angle within the range of about 20-60 degrees relative to a vertical.
13. The method of claim 1 , wherein forming said conductive contact comprises forming a conductive material in said opening and above said patterned hard mask layer.
14. A method, comprising: forming sacrificial gate structures for first and second spaced-apart transistors above a semiconducting substrate; forming an etch stop layer above said substrate and said sacrificial gate structures for said transistors; performing at least one angled ion implant process to implant at least one first etch-inhibiting species into less than an entirety of said etch stop layer; after performing said at least one angled ion implant process, forming a layer of insulating material above said etch stop layer; performing at least one chemical mechanical polishing process to expose at least a portion of each of said sacrificial gate structures; performing at least one first etching process to remove said sacrificial gate structures and thereby define a plurality of gate cavities; forming a replacement gate structure in each of said cavities; forming a hard mask layer above said replacement gate structures and said layer of insulating material; forming a patterned implant mask layer above said hard mask layer, said patterned implant mask layer exposing first portions of said hard mask layer and masking second portions of said hard mask layer; performing at least one ion implant process through said patterned implant mask layer to selectively implant at least one second etch-inhibiting species into said first portions only of said hard mask layer; after removing said implant mask layer, performing a second etching process on said hard mask layer to selectively remove said second portions only of said hard mask layer and thereby define a patterned hard mask layer; performing at least one third etching process through said patterned hard mask layer to define an opening in said layer of insulating material and thereby expose a portion of said etch stop layer; performing at least one fourth etching process on said exposed portion of said etch stop layer to define a contact opening therethrough that exposes a doped region formed in said substrate; and forming a conductive contact in said opening that is conductively coupled to said doped region.
15. The method of claim 14 , wherein performing said second etching process and said fourth etching process comprises performing a wet etching process or a dry, plasma-based etching process.
16. The method of claim 14 , wherein said first and second etch-inhibiting species are a polymer-forming species and wherein performing said second etching process and said fourth etching process comprises performing a dry, plasma-based etching process that causes formation of a polymer material proximate where said polymer-forming species have been implanted into said etch stop layer and said first portions of said hard mask layer, respectively.
17. The method of claim 14 , wherein performing said second etching process and said fourth etching process comprises performing a carbon-fluorine based plasma etching process.
18. The method of claim 14 , wherein performing said second etching process and said fourth etching process comprises performing a plasma etching process using at least one of the following process gases: C 4 F 8 /CH 2 F 2 /Ar, C 4 F 6 /CO/Ar, C 4 F 6 , or C 5 F 8 and nitrogen.
19. The method of claim 14 , wherein said first and second etch-inhibiting species are polymer-forming species and wherein performing said second etching process and said fourth etching process comprises performing a wet etching process that causes formation of a protective interfacial layer proximate where said first and second polymer-forming species have been implanted into said etch stop layer and said first portions of said hard mask layer, respectively.
20. The method of claim 14 , wherein said at least one angled implant process is performed at an angle such that said first transistor prevents the implantation of said at least one first etch-inhibiting species into the entirety of the etch stop layer positioned proximate a side of said second transistor.
21. The method of claim 14 , wherein said at least one angled implant process is performed at an angle such that a portion of said etch stop layer between said first and second transistors is not implanted with said first etch-inhibiting species.
22. The method of claim 14 , wherein said at least one angled implant process is performed at an angle such that portions of said etch stop layer within a vertical distance above a surface of said substrate that corresponds to approximately 30% of a gate height of one of said sacrificial gate structures is not implanted with said first etch-inhibiting species.
23. The method of claim 22 , wherein said vertical distance is about 40 nm or less.
24. The method of claim 14 , wherein said at least one angled implant process is performed at an angle such that only portions of said etch stop layer that are positioned a vertical distance above a surface of said substrate that is greater than a distance that corresponds to approximately 30% of a gate height of one of said sacrificial gate structures is implanted with said first etch-inhibiting species.
25. The method of claim 14 , wherein said angled ion implant process is performed at an angle within the range of about 20-60 degrees relative to a vertical.
26. A method, comprising: forming sacrificial gate structures for first and second spaced-apart transistors above a semiconducting substrate; forming an etch stop layer above said substrate and said sacrificial gate structures for said transistors; performing at least one angled ion implant process to implant at least one polymer-forming species into less than an entirety of said etch stop layer; after performing said at least one angled ion implant process, forming a layer of insulating material above said etch stop layer; performing at least one chemical mechanical polishing process to expose at least a portion of each of said sacrificial gate structures; performing at least one first etching process to remove said sacrificial gate structures and thereby define a plurality of gate cavities; forming a replacement gate structure in each of said cavities; forming a hard mask layer above said replacement gate structures and said layer of insulating material; performing a second etching process on said hard mask layer to define a patterned hard mask layer, wherein an entire upper surface of said hard mask layer is exposed to said second etching process; performing at least one third etching process through said patterned hard mask layer to define an opening in said layer of insulating material and thereby expose a portion of said etch stop layer; performing a dry, plasma-based etching process on said exposed portion of said etch stop layer to define a contact opening therethrough that exposes a doped region formed in said substrate, wherein performing said dry, plasma-based etching process causes formation of a polymer material proximate where said polymer-forming species have been implanted into said etch stop layer; and forming a conductive contact in said opening that is conductively coupled to said doped region.
27. The method of claim 26 , wherein performing said dry, plasma-based etching process on said etch stop layer comprises performing a carbon-fluorine based plasma etching process on said etch stop layer.
28. The method of claim 27 , wherein performing said dry, plasma-based process comprises performing a dry plasma etching process using at least one of the following process gases: C 4 F 8 /CH 2 F 2 /Ar, C 4 F 6 /CO/Ar, C 4 F 6 , or C 5 F 8 and nitrogen.
29. The method of claim 26 , wherein said at least one angled implant process is performed at an angle such that said first transistor prevents the implantation of said at least one polymer-forming species into the entirety of the etch stop layer positioned proximate a side of said second transistor.
30. The method of claim 26 , wherein said at least one angled implant process is performed at an angle such that a portion of said etch stop layer between said first and second transistors is not implanted with said polymer-forming species.
31. The method of claim 26 , wherein said at least one angled implant process is performed at an angle such that portions of said etch stop layer within a vertical distance above a surface of said substrate that corresponds to approximately 30% of a gate height of one of said sacrificial gate structures is not implanted with said polymer-forming species.
32. The method of claim 31 , wherein said vertical distance is about 40 nm or less.
33. The method of claim 26 , wherein said at least one angled implant process is performed at an angle such that only portions of said etch stop layer that are positioned a vertical distance above a surface of said substrate that is greater than a distance that corresponds to approximately 30% of a gate height of one of said sacrificial gate structures is implanted with said polymer-forming species.
34. The method of claim 26 , wherein forming said conductive contact comprises forming a conductive material in said opening and above said patterned hard mask layer.
35. A method, comprising: forming sacrificial gate structures for first and second spaced-apart transistors above a semiconducting substrate; forming an etch stop layer above said substrate and said sacrificial gate structures for said transistors; performing at least one angled ion implant process to implant at least one first polymer-forming species into less than an entirety of said etch stop layer; after performing said at least one angled ion implant process, forming a layer of insulating material above said etch stop layer; performing at least one chemical mechanical polishing process to expose at least a portion of each of said sacrificial gate structures; performing at least one first etching process to remove said sacrificial gate structures and thereby define a plurality of gate cavities; forming a replacement gate structure in each of said cavities; forming a hard mask layer above said replacement gate structures and said layer of insulating material; forming a patterned implant mask layer above said hard mask layer, said patterned implant mask layer exposing first portions of said hard mask layer and masking second portions of said hard mask layer; performing at least one ion implant process through said patterned implant mask layer to selectively implant at least one second polymer-forming species into said first portions only of said hard mask layer; after removing said implant mask layer, performing a first dry, plasma-based etching process on said hard mask layer to selectively remove said second portions only of said hard mask layer and thereby define a patterned hard mask layer, wherein performing said first dry, plasma-based etching process causes formation of a first polymer material proximate where said second polymer-forming species have been implanted into said first portions of said hard mask layer; performing at least one third etching process through said patterned hard mask layer to define an opening in said layer of insulating material and thereby expose a portion of said etch stop layer; performing a second dry, plasma-based etching process on said exposed portion of said etch stop layer to define a contact opening therethrough that exposes a doped region formed in said substrate, wherein performing said second dry, plasma-based etching process causes formation of a second polymer material proximate where said first polymer-forming species have been implanted into said etch stop layer; and forming a conductive contact in said opening that is conductively coupled to said doped region.
36. The method of claim 35 , wherein performing said first and second dry, plasma-based etching processes comprises performing carbon-fluorine based plasma etching processes.
37. The method of claim 35 , wherein performing said first and second dry, plasma-based etching processes comprises performing plasma etching processes using at least one of the following process gases: C 4 F 8 /CH 2 F 2 /Ar, C 4 F 6 /CO/Ar, C 4 F 6 , or C 5 F 8 and nitrogen.
38. The method of claim 35 , wherein said at least one angled implant process is performed at an angle such that said first transistor prevents the implantation of said at least one first polymer-forming species into the entirety of the etch stop layer positioned proximate a side of said second transistor.
39. The method of claim 35 , wherein said at least one angled implant process is performed at an angle such that a portion of said etch stop layer between said first and second transistors is not implanted with said at least one first polymer-forming species.
40. The method of claim 35 , wherein said at least one angled implant process is performed at an angle such that portions of said etch stop layer within a vertical distance above a surface of said substrate that corresponds to approximately 30% of a gate height of one of said sacrificial gate structures is not implanted with said at least one first polymer-forming species.
41. The method of claim 40 , wherein said vertical distance is about 40 nm or less.
42. The method of claim 35 , wherein said at least one angled implant process is performed at an angle such that only portions of said etch stop layer that are positioned a vertical distance above a surface of said substrate that is greater than a distance that corresponds to approximately 30% of a gate height of one of said sacrificial gate structures is implanted with said at least one first polymer-forming species.
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April 25, 2012
July 8, 2014
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