A method of manufacturing a semiconductor device includes providing a substrate having a gate structure, a source region, and a drain region formed thereon, and the gate structure includes a gate insulating layer and a gate electrode. The method also includes forming a first stress layer on the substrate, removing the first stress layer, and forming a second stress layer on the substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor device, the method comprising: providing a substrate having a gate structure, a source region, and a drain region formed thereon, the gate structure including a gate insulating layer and a gate electrode; forming a first stress layer on the substrate to cover the gate structure, the source region, and the drain region; removing the first stress layer; and forming a second stress layer on the substrate, wherein removing the first stress layer includes removing substantially an entirety of the first stress layer such that the second stress layer covers the gate structure, the source region, and the drain region.
2. The method as claimed in claim 1 , wherein both the first stress layer and the second stress layer provide a same type of stress from among a compressive stress and a tensile stress such that the first and second stress layers exert the same type of stress on a channel region, the channel region being between the source region and the drain region of the substrate.
3. The method as claimed in claim 1 , wherein, prior to forming the second stress layer, forming of the first stress layer and removing of the first stress layer are performed a plurality of times.
4. The method as claimed in claim 1 , further comprising, prior to forming the first stress layer and prior to forming the second stress layer, forming a buffer layer including a material having etch selectivity with respect to each of the first stress layer and the second stress layer.
5. The method as claimed in claim 1 , wherein the first stress layer and the second stress layer both include a silicon nitride.
6. The method as claimed in claim 5 , wherein forming the first stress layer and forming the second stress layer both include: depositing the silicon nitride, and irradiating ultra violet rays to the silicon nitride.
7. The method as claimed in claim 5 , wherein depositing the silicon nitride for forming the first stress layer and depositing the silicon nitride for forming the second stress layer include performing ion bombardment on the silicon nitride.
8. The method as claimed in claim 1 , wherein: the gate insulating layer includes a material with a high dielectric constant, and the gate electrode includes a metal.
9. The method as claimed in claim 1 , further comprising, prior to forming the first stress layer, forming a metal silicide layer on the gate electrode, the source region, and the drain region.
10. The method as claimed in claim 9 , wherein forming the metal silicide layer includes: forming a metal layer on the gate structure, the source region, and the drain region, heat-treating the metal layer to selectively form the metal silicide layer on the gate structure, the source region, and the drain region, and removing non-reacted portions of the metal layer, the non-reacted portions of the metal layer corresponding to portions of the metal layer excluded from the metal silicide layer.
11. The method as claimed in claim 1 , further comprising: forming an interlayer insulating layer on the substrate; and forming contact plugs on the source region and the drain region by using the second stress layer as an etch stop layer.
12. The method as claimed in claim 1 , wherein, when a stress exerted on a channel region between the source region and the drain region is a tensile stress, the tensile stress is equal to or greater than about 1.5 GPa.
13. A method of manufacturing a semiconductor device, the method comprising: providing a substrate having a gate electrode, a source region, and a drain region formed thereon; forming an etch stop layer for forming contact plugs that are connected to the source region and the drain region, respectively, on the substrate, the etch stop layer covering the gate structure, the source region, and the drain region; removing the etch stop layer; and forming an additional etch stop layer on the substrate, wherein removing the etch stop layer includes removing substantially an entirety of the etch stop layer such that the additional etch stop layer covers the gate structure, the source region, and the drain region.
14. The method as claimed in claim 13 , wherein the etch stop layer and the additional etch stop layer contain a stress therein.
15. A method of manufacturing a semiconductor device, the method comprising: providing a substrate having a gate structure, a source region, and a drain region formed thereon, the gate structure including a gate insulating layer and a gate electrode; forming a first stress layer on the substrate to cover the gate structure, the source region, and the drain region; removing the first stress layer; forming a second stress layer on the substrate after removing the first stress layer; forming an interlayer insulating layer on the second stress layer; and forming contact holes in the interlayer insulating layer by using the second stress layer as an etch stop layer, wherein removing the first stress layer includes removing substantially an entirety of the first stress layer such that the second stress layer covers the gate structure, the source region, and the drain region.
16. The method as claimed in claim 15 , wherein: the substrate includes a channel region between the source region and the drain region, and the first stress layer and the second stress layer apply a same type of stress to the channel region.
17. The method as claimed in claim 15 , further comprising forming a third stress layer and a fourth stress layer before forming the interlayer insulating layer, wherein: the gate structure, the source region, and the drain region are one of a plurality of gate structures, a plurality of source regions, and a plurality of drain regions, respectively, the substrate includes a NMOS region and a PMOS region each having formed therein at least one of the plurality of gate structures, at least one of the plurality of source regions, and at least one of the plurality of drain regions, the first stress layer and the second stress layer apply a first type of stress to one channel region in one of the NMOS region and the PMOS region, and the third stress layer and the fourth stress layer apply a second type of stress to another channel region in another of the NMOS region and the PMOS region, the second type of stress being different from the first type of stress.
18. A method of manufacturing a semiconductor device, the method comprising: providing a substrate having a gate structure, a source region, and a drain region formed thereon, the gate structure including a gate insulating layer and a gate electrode; forming a first stress layer on the substrate; removing an upper thickness portion of the first stress layer such that a remaining thickness portion of first stress layer on the substrate has a predetermined thickness; and forming a second stress layer substantially covering an entirety of the first stress layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 1, 2012
July 8, 2014
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