Patentable/Patents/US-8773788
US-8773788

Systems and methods for hardware assisted write pre-compensation enhancement

PublishedJuly 8, 2014
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

Various embodiments of the present invention provide systems and methods for calibrating write pre-compensation values.

Patent Claims
21 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A storage device, the storage device comprising: a storage medium including a region and at least a first sub-region and a second sub-region within the region; a calibration circuit operable to: generate a first pre-compensation value and a second pre-compensation value; write data to the first sub-region using the first pre-compensation value; write data to the second sub-region using the second pre-compensation value; read the first sub-region; calculate a first quality of a data set read from the first sub-region; read the second sub-region; calculate a second quality of a data set read from the second sub-region; and compare the first quality with the second quality to yield a compare value, and based at least in part on the compare value, select one of the first pre-compensation value and the second pre-compensation value as a selected pre-compensation value.

2

2. The storage device of claim 1 , wherein the first quality is selected from a group consisting of: a bit error rate of the first sub-region, a sum of the log-likelihood ratio values within the first sub-region, and a minimum mean squared error value within the first sub-region.

3

3. The storage device of claim 1 , wherein the device further comprises: a memory operable to store the selected pre-compensation value.

4

4. The storage device of claim 1 , wherein the calibration circuit is implemented as part of an integrated circuit.

5

5. The storage device of claim 1 , wherein the storage device further comprises: a solid state memory.

6

6. The storage device of claim 1 , wherein the calibration circuit includes a counter circuit, and wherein the counter circuit is incremented to generate the first pre-compensation value and the second pre-compensation value.

7

7. The storage device of claim 1 , wherein the first quality indicates a greater quality than the second quality, and wherein the first pre-compensation value is selected as the selected pre-compensation value.

8

8. The storage device of claim 1 , wherein the region is a track on the storage medium, and wherein the first sub-region is a first sector on the track and the second sub-region is a second sector on the track.

9

9. The storage device of claim 1 , wherein the selected pre-compensation value is a first selected pre-compensation value, wherein the region is a first region, wherein the storage medium includes a second region comprising at least a third sub-region and a fourth sub-region within the second region, and wherein the calibration circuit is further operable to: generate a third pre-compensation value and a fourth pre-compensation value; write data to the third sub-region using the third pre-compensation value; write data to the fourth sub-region using the fourth pre-compensation value; read the third sub-region; calculate a third quality of a data set read from the third sub-region; read the fourth sub-region; calculate a fourth quality of a data set read from the fourth sub-region; and based at least in part on the third quality and the fourth quality, selecting one of the third pre-compensation value and the fourth pre-compensation value as a second selected pre-compensation value.

10

10. The storage device of claim 1 , wherein the storage device is included as part of a redundant array of independent disks.

11

11. A calibration circuit, the circuit comprising: a counter circuit operable to generate a first pre-compensation value corresponding to a first count output of the counter circuit, and to generate a second pre-compensation value corresponding to a second count output of the counter circuit; a write circuit operable to: write data to a first region of a storage medium using the first pre-compensation value; and write data to a second region of the storage medium using the second pre-compensation value; a read circuit operable to: read the first region to yield a first read data set, and to calculate a first quality corresponding to the first data set; read the second region to yield a second read data set, and to calculate a first quality corresponding to the first data set; a pre-compensation value selector circuit operable to compare the first quality with the second quality to yield a compare value, and select one of the first pre-compensation value and the second pre-compensation value based at least in part on the compare value.

12

12. The calibration circuit of claim 11 , wherein the calibration circuit is implemented as part of an integrated circuit.

13

13. The calibration circuit of claim 11 , wherein the calibration circuit further comprises: a memory operable to store the selected pre-compensation value.

14

14. The calibration circuit of claim 11 , wherein the first quality is selected from a group consisting of: a bit error rate of the first region, a sum of the log-likelihood ratio values within the first region, and a minimum mean squared error value within the first region; and wherein the second quality is selected from a group consisting of: a bit error rate of the second region, a sum of the log-likelihood ratio values within the second region, and a minimum mean squared error value within the second region.

15

15. The calibration circuit of claim 11 , wherein the first region is a first sector on the storage medium, and the second region is a second sector on the storage medium.

16

16. The calibration circuit of claim 11 , wherein the first quality indicates a greater quality than the second quality, and wherein the first pre-compensation value is selected as the selected pre-compensation value.

17

17. A method for pre-compensation calibration, the method comprising: generating a first pre-compensation value and a second pre-compensation value using a counter circuit; writing data to a first region of a storage medium using the first pre-compensation value; writing data to a second region of the storage medium using the second pre-compensation value; reading the first region to yield a first data set; calculating a first quality of the first data set; reading the second region to yield a second data set; calculating a second quality of the second data set; and comparing the first quality with the second quality to yield a compare value, and based at least in part on the compare value, selecting one of the first pre-compensation value and the second pre-compensation value as a selected pre-compensation value.

18

18. The method of claim 17 , wherein: the first quality is selected from a group consisting of: a bit error rate of the first region, a sum of the log-likelihood ratio values within the first region, and a minimum mean squared error value within the first region; and the second quality is selected from a group consisting of: a bit error rate of the second region, a sum of the log-likelihood ratio values within the second region, and a minimum mean squared error value within the second region.

19

19. The method of claim 17 , wherein the method further comprises: storing the selected pre-compensation value.

20

20. The method of claim 17 , wherein the first quality indicates a greater quality than the second quality, and wherein the first pre-compensation value is selected as the selected pre-compensation value.

21

21. The method of claim 17 , wherein the first region is a first sector on the storage medium, and the second region is a second sector on the storage medium.

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Patent Metadata

Filing Date

July 10, 2012

Publication Date

July 8, 2014

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