Single-event-upset resistant memory cell with triple well

1. A memory cell comprising: a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value, the plurality of transistors comprising: a first transistor of a first type in a first well of a second type having a first well tap connected to a source of the first transistor; a second transistor of the first type in a second well of the second type having a second well tap connected to a source of the second transistor; a third transistor of the second type in a third well of the first type having a third well tap connected to a source of the third transistor; and a fourth transistor of the second type in a fourth well of the first type having a fourth well tap connected to a source of the fourth transistor, the first well, second well, third well, and forth well being isolated from each other.

2. The memory cell of claim 1 wherein the first transistor, the second storage transistor, the third storage transistor, and the fourth storage transistor are configured to operate as a first inverter circuit.

3. The memory cell of claim 1 wherein the first well is formed in a first tub of the first type so as to form a first P-N junction between the first well and the first tub and the second well is formed in a second tub of the first type so as to form a second P-N junction between the second well and the second tub.

4. The memory cell of claim 3 wherein the first tub a P-type tub and the first well is an N-type well.

5. The memory cell of claim 3 further comprising a separator common to the first tub and to the second tub.

6. The memory cell of claim 1 wherein at least one of the first transistor, second transistor, third transistor and fourth transistor is a shielded transistor.

7. The memory cell of claim 1 further comprising an access transistor formed in a fifth well having a fifth well tap.

8. The memory cell of claim 1 wherein the first transistor is connected in series with the second transistor and the third transistor is connected in series with the fourth transistor.

9. The memory cell of claim 1 wherein the first transistor is connected in parallel with the second transistor.

10. The memory cell of claim 1 further comprising: a fifth transistor of the first type in a fifth well of the second type having a fifth well tap connected to a source of the fifth transistor; a sixth transistor of the first type in a sixth well of the second type having a sixth well tap connected to a source of the sixth transistor; a seventh storage transistor of the second type in a seventh well of the first type having a seventh well tap connected to a source of the seventh transistor; and an eighth storage transistor of the second type in an eighth well of the first type having an eighth well tap connected to a source of the eighth transistor, the fifth well, sixth well, seventh well and eighth well being isolated from each other and from each of the first well, the second well, the third well and the fourth well.

11. The memory cell of claim 10 wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are configured to operate as a first inverter circuit and the fifth transistor, the sixth transistor, the seventh transistor a second tub.

12. The memory cell of claim 10 wherein the first transistor is connected in series with the second transistor and the fifth transistor is connected in series with the sixth transistor.

13. The memory cell of claim 10 wherein the first transistor is connected in parallel with the second transistor.

14. The memory cell of claim 10 further comprising a first tub; and a second tub.

15. The memory cell of claim 14 further comprising a separator common to the first tub and the second tub.

16. The memory cell of claim 1 , wherein: the first and second well taps are electrically coupled to a positive supply voltage; and the third and forth well taps are electrically coupled to a ground voltage.

17. A memory cell, comprising: a first inverter including a first, a second, a third, and a fourth transistor, the first transistor serially connected to the second transistor, the third transistor serially connected to the fourth transistor, and the second transistor coupled to the third transistor; a second inverter cross-coupled to the first inverter to provide redundant storage and including a fifth, a sixth, a seventh, and an eighth transistor, the fifth transistor serially connected to the sixth transistor, the seventh transistor serially connected to the eighth transistor, and the sixth transistor coupled to the seventh transistor; wherein each of the first, second, fifth, and sixth transistors are of a first type and have respective well taps connected to respective sources of the transistors, and each of the third, fourth, seventh, and eighth transistors are of a second type and have respective well taps connected to respective sources of the transistors; and wherein each of the first, second, fifth, and sixth transistors are in respective wells of the second type, each of the third, fourth, seventh, and eighth transistors are in respective wells of the first type, and the respective wells are electrically isolated from one another.

18. The memory cell of claim 17 , wherein the second and third transistors are coupled in series, and the sixth and seventh transistors are coupled in series.

19. The memory cell of claim 17 , wherein the second and third transistors are coupled in parallel, and the sixth and seventh transistors are coupled in parallel.