A device includes a semiconductor substrate, and a channel region of a transistor over the semiconductor substrate. The channel region includes a semiconductor material. An air gap is disposed under and aligned to the channel region, with a bottom surface of the channel region exposed to the air gap. Insulation regions are disposed on opposite sides of the air gap, wherein a bottom surface of the channel region is higher than top surfaces of the insulation regions. A gate dielectric of the transistor is disposed on a top surface and sidewalls of the channel region. A gate electrode of the transistor is over the gate dielectric.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A device comprising: a semiconductor substrate; a channel region of a transistor over the semiconductor substrate, wherein the channel region comprises a semiconductor material; an air gap under and aligned to the channel region, with a bottom surface of the channel region exposed to the air gap; insulation regions on opposite sides of the air gap, wherein a bottom surface of the channel region is higher than top surfaces of the insulation regions; a gate dielectric of the transistor on a top surface and sidewalls of the channel region; and a gate electrode of the transistor over the gate dielectric.
2. The device of claim 1 , wherein the air gap extends into a space between the insulation regions.
3. The device of claim 1 , wherein the gate dielectric is in contact with opposite sidewalls of the channel region.
4. The device of claim 1 , wherein the channel region and the semiconductor substrate comprise different semiconductor materials.
5. The device of claim 1 , wherein the channel region comprises a top planar portion, and two edge portions below the top planar portion, wherein the two edge portions are connected to opposite sides of the top planar portion, and wherein sidewalls of the two edge portions are substantially perpendicular to a major top surface of the semiconductor substrate.
6. The device of claim 1 , wherein the channel region is planar, and wherein the channel region has a substantially planar top surface and a substantially planar bottom surface.
7. The device of claim 1 further comprising: a first semiconductor region connected to an end of the channel region, wherein the channel region and the first semiconductor region are formed of a same semiconductor material; and a second semiconductor region underlying and in contact with the first semiconductor region, wherein edges of the second semiconductor region are recessed from respective edges of the first semiconductor region, and wherein the first and the second semiconductor regions are formed of different semiconductor materials.
8. A device comprising: a semiconductor substrate; insulation regions at a top portion of semiconductor substrate, wherein the insulation regions comprise two sidewalls facing each other, and wherein the two sidewalls are spaced apart from each other by a space; a channel region comprising a semiconductor material over the semiconductor substrate and aligned to the space; an air gap underlying and aligned to the channel region, wherein the air gap comprises first edges substantially aligned to respective ones of the two sidewalls of the insulation regions; a gate dielectric on a top surface and sidewalls of the channel region; and a gate electrode over the gate dielectric, wherein the channel region, the gate dielectric, and the gate electrode form parts of a transistor, and wherein the air gap comprises a portion level with, and between, portions of the gate electrode that are on opposite sides of the air gap.
9. The device of claim 8 , wherein the air gap extends into the space, with upper portions of the two sidewalls of the insulation regions exposed to the air gap.
10. The device of claim 8 , wherein the channel region comprises a top planar portion, and two edge portions below the top planar portion, wherein the two edge portions are connected to opposite sides of the top planar portion, wherein each of the two edge portions comprises an inner edge facing, and level with, a portions of the air gap, and wherein the inner edge is a substantially straight edge substantially perpendicular to the major top surface of the semiconductor substrate.
11. The device of claim 8 , wherein each of the first edges and a respective one of the two sidewalls of the insulation regions are aligned to a same line that is perpendicular to a major top surface of the semiconductor substrate.
12. The device of claim 8 further comprising: a first semiconductor region connected to an end of the channel region, wherein the channel region and the first semiconductor region are formed of a same semiconductor material; and a second semiconductor region underlying in contact with the first semiconductor region, wherein edges of the second semiconductor region are recessed from respective edges of the first semiconductor region, and wherein the first and the second semiconductor regions are formed of different semiconductor materials.
13. The device of claim 8 , wherein the air gap further comprises second edges overlapping the insulation regions, and wherein a first distance between the first edges is smaller than a second distance between the second edges.
14. A device comprising: a semiconductor substrate; insulation regions extending into the semiconductor substrate; a first and a second epitaxy region spaced apart from each other, wherein the first and the second epitaxy regions extend from a level above top surfaces of the insulation regions into the insulation regions; a semiconductor layer above the top surfaces of the insulation regions, wherein opposite ends of the semiconductor layer is supported by the first and the second epitaxy regions, and wherein a center portion of the semiconductor layer is overlying an air gap, and wherein the air gap is between two portions of the insulation regions, and wherein opposite sidewalls of the two portions of the insulation regions are exposed to the air gap; a gate dielectric of a transistor on a top surface and sidewalls of the center portion of the semiconductor layer; and a gate electrode of the transistor over the gate dielectric.
15. The device of claim 14 , wherein a bottom surface of the semiconductor layer is exposed to the air gap.
16. The device of claim 14 , wherein a portion of the semiconductor layer overlaps an entirety of the space between the opposite sidewalls of the two portions of the insulation regions.
17. The device of claim 14 , wherein the gate dielectric is in contact with opposite sidewalls of the semiconductor layer.
18. The device of claim 14 , wherein the semiconductor layer and the first and the second epitaxy regions comprise different semiconductor materials.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 30, 2012
July 15, 2014
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