A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a first conductive layer including a first area isolated from a second area of the first conductive layer; a conductive pillar formed over a first surface of the first area of the first conductive layer; a semiconductor die or component disposed over a first surface of the second area of the first conductive layer; and a conductive bridge formed contacting a second surface of the second area of the first conductive layer opposite the first surface of the second area and a second surface of the first area of the first conductive layer opposite the first surface of the first area.
2. The semiconductor device of claim 1 , wherein the first conductive layer includes a plurality of conductive layers.
3. The semiconductor device of claim 1 , further including a second conductive layer formed over the first conductive layer.
4. The semiconductor device of claim 1 , wherein the conductive bridge includes a second conductive layer including a plurality of conductive layers.
5. The semiconductor device of claim 1 , further including: an encapsulant deposited over the semiconductor die and around the conductive pillar; a first insulating layer formed over the encapsulant; a second conductive layer formed over the first insulating layer, the second conductive layer being electrically connected to the conductive pillar; and a second insulating layer formed over the second conductive layer.
6. The semiconductor device of claim 1 , wherein the first conductive layer includes an interconnect line and under bump metallization pad.
7. The semiconductor device of claim 1 , further including a bump formed over the conductive pillar.
8. The semiconductor device of claim 1 , wherein the conductive bridge includes a bump.
9. A semiconductor device, comprising: a first conductive layer including a gap between a first area of the first conductive layer and a second area of the first conductive layer; a conductive pillar formed over the first area of the first conductive layer; a semiconductor die disposed over a first surface of the second area of the first conductive layer; and a second conductive layer formed over the first area of the first conductive layer and a second surface of the second area of the first conductive layer opposite the first surface of the second area.
10. The semiconductor device of claim 9 , further including a first encapsulant deposited over the semiconductor die and around the conductive pillar.
11. The semiconductor device of claim 9 , wherein the first conductive layer includes an interconnect line and under bump metallization pad.
12. The semiconductor device of claim 9 , wherein the first conductive layer includes a plurality of conductive layers.
13. The semiconductor device of claim 9 , further including a third conductive layer formed over the first conductive layer.
14. The semiconductor device of claim 13 , wherein the third conductive layer includes a plurality of conductive layers.
15. The semiconductor device of claim 9 , further including an interconnect structure formed over the conductive pillar.
16. The semiconductor device of claim 10 , further including a second encapsulant deposited over the first encapsulant.
17. The semiconductor device of claim 9 , wherein the second conductive layer includes a bump.
18. A semiconductor device, comprising: a conductive layer including a first area isolated from a second area of the conductive layer; a conductive pillar disposed over the first area of the conductive layer; a semiconductor die or component disposed over the second area of the conductive layer; and a first bump formed over the first area of the conductive layer and the second area of the conductive layer.
19. The semiconductor device of claim 18 , further including a first encapsulant deposited over the semiconductor die and around the conductive pillar.
20. The semiconductor device of claim 18 , further including a second bump formed over the conductive pillar.
21. The semiconductor device of claim 19 , further including a second encapsulant deposited over the first encapsulant.
22. A semiconductor device, comprising: a first conductive layer including an interconnect line and under bump metallization pad; a conductive pillar formed over the first conductive layer; a semiconductor die disposed over the first conductive layer; and a bump formed over the first conductive layer electrically connecting the interconnect line and under bump metallization pad.
23. The semiconductor device of claim 22 , further including a solder bump formed over the conductive pillar.
24. The semiconductor device of claim 22 , further including: a first encapsulant deposited over the semiconductor die and around the conductive pillar; and a second encapsulant deposited over the first encapsulant.
25. The semiconductor device of claim 22 , wherein the first conductive layer includes a plurality of conductive layers.
26. The semiconductor device of claim 22 , further including forming a second conductive layer over the first conductive layer, the second conductive layer including a plurality of conductive layers.
27. The semiconductor device of claim 5 , further including an interconnect structure formed over the encapsulant, the interconnect structure being electrically connected to the conductive pillar.
28. The semiconductor device of claim 6 , wherein the interconnect line includes a solder bridge.
29. The semiconductor device of claim 10 , further including an interconnect structure formed over the first encapsulant, the interconnect structure being electrically connected to the conductive pillar.
30. The semiconductor device of claim 11 , wherein the interconnect line includes a solder bridge.
31. The semiconductor device of claim 19 , further including an interconnect structure formed over the first encapsulant, the interconnect structure being electrically connected to the conductive pillar.
32. The semiconductor device of claim 24 , further including an interconnect structure formed over the first encapsulant, the interconnect structure being electrically connected to the conductive pillar.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 2, 2009
August 5, 2014
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