A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording valid/invalid page position information of at least one block; and moving valid data contained in at least a valid page of the block according to the valid/invalid page position information; where the block is an erasing unit. For example, the valid/invalid page position information may contain relative position information of the valid data in the block. More particularly, the valid/invalid page position information may contain a plurality of bits, the ranking of each bit may represent a page address offset of each page within the block, and each bit may respectively indicate whether each page in the block is valid or invalid.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for managing a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element, each of which comprises a plurality of blocks comprising a plurality of pages, respectively, the method comprising: recording valid/invalid page position information of at least one block, wherein the block comprises valid pages and invalid pages, and the valid/invalid page position information indicates that each of the pages of the block is a valid page or an invalid page; and moving valid data contained in at least a valid page of the block according to the valid/invalid page position information; wherein the block is an erasing unit.
2. The method of claim 1 , wherein the valid/invalid page position information contains relative position information of the valid data in the block.
3. The method of claim 2 , wherein the valid/invalid page position information contains a plurality of bits, the ranking of each bit represents a page address offset of each page within the block, and each bit respectively indicates whether each page in the block is valid or invalid.
4. The method of claim 1 , further comprising: storing the valid/invalid page position information into the NV memory element before shutting down the memory apparatus.
5. The method of claim 1 , wherein the step of recording the valid/invalid page position information of the at least one block further comprises: searching a page address linking table after turning on the memory apparatus and update a global page address linking table; and building a valid page position table comprising the valid/invalid page position information according to the updated global page address linking table.
6. The method of claim 1 , wherein for each page of the block, the valid/invalid page position information provides a single bit to indicate that the page is a valid page or an invalid page, and one of logical values “0” and “1” is used to represent that the page is valid, and the other one of the logical values “0” and “1” is used to represent that the page is invalid.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 8, 2012
August 5, 2014
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