Some of the embodiments of the present disclosure provide a integrated circuit comprising a plurality of components, wherein each of the plurality of components is configured to receive a clock signal and a reset signal; a clock module configured to selectively suppress the clock signal; and a reset module configured to assert the reset signal while the clock signal is suppressed. Other embodiments are also described and claimed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit comprising: a plurality of components, wherein each of the plurality of components is configured to receive a clock signal and a reset signal; a reset module configured to (i) assert the reset signal subsequent to a trigger event and prior to a commencement of a first time period, (ii) assert the reset signal during the first time period, and (ii) de-assert the reset signal following the first time period; and a clock module configured to (i) suppress the clock signal during the first time period, and (ii) refrain from suppressing the clock signal subsequent to the trigger event and prior to the commencement of the first time period.
2. The integrated circuit of claim 1 , wherein: in response to the trigger event, (i) the clock module is configured to selectively suppress the clock signal and (ii) the reset module is configured to assert the reset signal; and the trigger event comprises one or more of a start-up of the integrated circuit, a resetting of the integrated circuit, and a resetting of the clock module.
3. The integrated circuit of claim 1 , wherein: the clock module is further configured to suppress the clock signal during a second time period that commences subsequent to an end of the first time period; and the reset module is further configured to keep the reset signal de-asserted during the second time period.
4. The integrated circuit of claim 3 , wherein (i) the first time period and (ii) the second time period are based on a time taken by the reset signal to reach the plurality of components.
5. The integrated circuit of claim 3 , wherein: the clock module is further configured to refrain from suppressing the clock signal during a third time period that commences subsequent to an end of the second time period; and the reset module is further configured to keep the reset signal de-asserted during the third time period.
6. The integrated circuit of claim 1 , further comprising: a reset tree configured to distribute the reset signal to the plurality of components, the reset tree being an unbalanced signal tree; and a clock tree configured to distribute the clock signal to the plurality of components, the clock tree being a balanced signal tree.
7. The integrated circuit of claim 1 , wherein one or more of the plurality of components comprise one or more of flip-flops, macros and counters.
8. The integrated circuit of claim 1 , wherein the reset signal is one of a synchronous reset signal and an asynchronous reset signal.
9. The integrated circuit of claim 1 , wherein each of the plurality of components is reset when the corresponding component receives the asserted reset signal.
10. A method comprising: transmitting, to a plurality of components of an integrated circuit, a clock signal and a reset signal; asserting the reset signal (i) subsequent to a trigger event and prior to a commencement of a first time period, and (ii) during the first time period; de-asserting the reset signal following the first time period; suppressing the clock signal during the first time period; and refraining from suppressing the clock signal subsequent to the trigger event and prior to the commencement of the first time period.
11. The method of claim 10 , further comprising: detecting the trigger event.
12. The method of claim 10 , further comprising: during a second time period that commences subsequent to an end of the first time period, suppressing the clock signal; and during the second time period, de-asserting the reset signal.
13. The method of claim 12 , further comprising: during a third time period that commences subsequent to an end of the second time period, refraining from suppressing the clock signal; and during the third time period, de-asserting the reset signal.
14. The method of claim 10 , wherein: transmitting the reset signal further comprises transmitting the reset signal to the plurality of components via a reset signal tree, the reset signal tree being an unbalanced signal tree; and transmitting the clock signal further comprises transmitting the clock signal to the plurality of components via a clock signal tree, the clock signal tree being a balanced signal tree.
15. A method comprising: distributing a reset signal to a plurality of components of an integrated circuit via a reset signal tree, the reset signal tree being an unbalanced signal tree; distributing a clock signal to the plurality of components of the integrated circuit via a clock signal tree, the clock signal tree being a balanced signal tree; resetting the plurality of components, by an assertion of the reset signal, such that each of the plurality of components comes out of reset during a same clock cycle; detecting a start-up event of the integrated circuit; in response to detecting the start-up event, selectively suppressing the clock signal; in response to detecting the start-up event, asserting the reset signal when the clock signal is selectively suppressed; and in response to detecting the start-up event, asserting the reset signal when the clock signal is not suppressed.
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January 17, 2012
August 12, 2014
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