Described herein is a wireless transceiver and related method that enables ultra low power transmission and reception of wireless communications. In an example embodiment of the wireless transceiver, the wireless transceiver receives a first-reference signal having a first-reference frequency. The wireless transceiver then uses the first-reference signal to injection lock a local oscillator, which provides a set of oscillation signals each having an oscillation frequency that is equal to the first-reference frequency, and each having equally spaced phases. Then the wireless transceiver combines the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency (in accordance with a transmitter implementation) or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first-reference frequency (in accordance with a receiver implementation).
Legal claims defining the scope of protection, as filed with the USPTO.
1. A circuit comprising: an oscillator circuit configured to provide a set of oscillation signals, each oscillation signal having an oscillation frequency; an injection-locking circuit coupled to the oscillator circuit, wherein the injection-locking circuit is configured to (i) receive a first-reference signal having a first-reference frequency and (ii) use the first-reference signal to injection lock the oscillator circuit, such that the oscillation frequency is equal to the first-reference frequency; and an edge-combining circuit coupled to the oscillator circuit, wherein the edge-combining circuit is configured to combine the set of oscillation signals into an output signal, wherein the output signal has an output frequency that is one of (i) a multiple of the first-reference frequency or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first-reference frequency.
2. The circuit of claim 1 , wherein the oscillator circuit comprises a ring-oscillator circuit having a set of delay elements, and wherein the ring-oscillator circuit is configured to provide a respective one of the set of oscillation signals at an output of a respective one of the set of delay elements.
3. The circuit of claim 2 , wherein the edge-combining circuit is further configured to receive the oscillation signals provided by the ring-oscillator circuit at the outputs of the set of delay elements.
4. The circuit of claim 1 , wherein the first-reference signal has a period T, wherein the set of oscillation signals comprises oscillation signals A 1 , A 2 . . . A N , wherein each of the oscillation signals A 1 , A 2 . . . A N has a respective phase, and wherein the respective phases are equally spaced apart by a period of T/(2N).
5. The circuit of claim 4 , wherein the output frequency is the multiple of the first-reference frequency, and wherein the edge-combining circuit being configured to combine the set of oscillation signals into the output signal comprises the edge-combining circuit being configured to: generate a set of signal products A 1 A 2 , A 2 A 3 . . . A N A 1 ; and generate a summation of the set of signal products to produce the output signal having an output frequency equal to the first-reference frequency multiplied by N.
6. The circuit of claim 4 , wherein the output frequency is the difference frequency, and wherein the edge-combining circuit being configured to combine the set of oscillation signals into the output signal comprises the edge-combining circuit being configured to: generate a set of signal products A 1 A 2 , A 2 A 3 . . . A N A 1 ; mix the set of signal products with the second-reference signal; and generate a summation of the mixed set of signal products to produce the output signal having an output frequency equal to the difference frequency.
7. The circuit of claim 1 , wherein the first-reference signal is a frequency-shift keyed (FSK) reference-clock signal.
8. The circuit of claim 1 , the circuit further comprising: a wireless-transmitter circuit coupled to the edge-combining circuit, wherein the wireless-transmitter circuit is configured to wirelessly transmit the output signal.
9. The circuit of claim 1 , wherein the first-reference signal is a reference-clock signal.
10. The circuit of claim 1 , the circuit further comprising: a wireless-receiver circuit coupled to the edge-combining circuit, wherein the wireless-receiver circuit is configured to wirelessly receive the second-reference signal.
11. The circuit of claim 1 , wherein the second-reference signal is a modulated signal, the circuit further comprising: a demodulation circuit coupled to the edge-combining circuit, wherein the demodulation circuit is configured to demodulate the output signal.
12. The circuit of claim 1 , wherein the output frequency is a frequency within one of the ranges of 6.765-6.795 MHz, 13.553-13.567 MHz, 26.957-27.283 MHz, 40.66-40.70 MHz, 433.05-434.79 MHz, 902-928 MHz, 2.400-2.500 GHz, 5.725-5.875 GHz.
13. The circuit of claim 1 , wherein the injection-locking circuit comprises at least a first stage and a second stage, wherein the first stage is configured to provide a single-phase injection of the reference frequency to the oscillator circuit, and wherein the second stage is configured to provide a multi-phase symmetrical injection of the reference frequency to the oscillator circuit.
14. A method comprising: receiving a first-reference signal having a first-reference frequency; using the first-reference signal to injection lock a local oscillator that provides a set of oscillation signals each having an oscillation frequency, such that the oscillation frequency is equal to the first-reference frequency; and combining the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first-reference frequency.
15. The method of claim 14 , wherein the first-reference signal has a period T, wherein the set of oscillation signals comprises oscillation signals A 1 , A 2 . . . A N , wherein each of the oscillation signals A 1 , A 2 . . . A N has a respective phase, and wherein the respective phases are equally spaced apart by a period of T/(2N).
16. The method of claim 15 , wherein the output frequency is the multiple of the first-reference frequency, and wherein combining the set of oscillation signals into the output signal having the output frequency comprises: generating a set of signal products A 1 A 2 , A 2 A 3 . . . A N A 1 ; and generating a summation of the set of signal products to produce the output signal having an output frequency equal to the reference frequency multiplied by N.
17. The method of claim 15 , wherein the output frequency is the difference frequency, and wherein combining the set of oscillation signals into the output signal having the output frequency comprises: generating a set of signal products A 1 A 2 , A 2 A 3 . . . A N A 1 ; mixing the set of signal products with the second-reference signal; and generating a summation of the mixed set of signal products to produce the output signal having an output frequency equal to the difference frequency.
18. The method of claim 14 , wherein the first-reference signal is a frequency-shift keyed (FSK) reference-clock signal, the method further comprising: wirelessly transmitting the output signal.
19. An apparatus comprising: means for providing a set of oscillation signals, each oscillation signal having an oscillation frequency; means for injection locking comprising means for (i) receiving a first-reference signal having a first-reference frequency and (ii) use the first-reference signal to injection lock the oscillator circuit, such that the oscillation frequency is equal to the first-reference frequency; and means for combining the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency or (ii) a difference frequency that is a difference of (a) a second-reference frequency of a second-reference signal and (b) the multiple of the first-reference frequency.
20. The apparatus of claim 19 , wherein the means for injection locking further comprise (i) means for providing a single phase injection of the reference signal to the means for providing a set of oscillation signals and (ii) means for providing a multi-phase symmetrical injection of the reference signal to the means for providing a set of oscillation signals.
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March 23, 2011
August 19, 2014
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