Customizing a target system. The target system may include a first device with a first programmable hardware element (PHE) and a second device with a second PHE. Synchronization modules may be provided for implementation on the first and second PHEs. The synchronization modules may provide a standard interface for interacting with other code. A user may specify user-created code for the first and second PHEs which utilizes the synchronization modules. The user-created code may interact with the synchronization modules using the standard interface. Accordingly, hardware descriptions may be generated for the first and second PHEs of the target system. Different modules may be used for different interconnects. Additionally, multiple synchronization modules may be used, e.g., dynamically, during operation of the target system.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for customizing a test instrument, wherein the test instrument comprises at least a first device with a first programmable hardware element (PHE) and a second device with a second PHE, comprising: providing a first synchronization module, wherein the first synchronization module comprises code for implementation on the first PHE of the first device, wherein the first synchronization module provides a standard interface for interacting with other code; storing first user-created code which performs a first function; receiving user input associating the first synchronization module with the first user-created code, wherein the first user-code is configured to interact with the first synchronization module using the standard interface; providing a second synchronization module, wherein the second synchronization module comprises code for implementation on the second PHE of the second device, wherein the second synchronization module provides the standard interface for interacting with other code; storing second user-created code which performs a second function; receiving user input associating the second synchronization module with the second user-created code, wherein the second user-created code is configured to interact with the second synchronization module using the standard interface; generating a first hardware description based on the first synchronization module and the associated first user-created code; generating a second hardware description based on the second synchronization module and the associated second user-created code; wherein the first synchronization module in the first hardware description and the second synchronization module in the second hardware description are configured to synchronize the first user-created code and the second user-created code, and wherein for each of the first and second synchronization modules, the standard interface allows swapping out the synchronization module without requiring modification of the associated user-created code.
2. The method of claim 1 , wherein the first user-created code and the second user-created code utilize a plurality of custom triggers, wherein each custom trigger is invoked and received using the first and second synchronization modules.
3. The method of claim 1 , wherein the first and second synchronization modules are instantiations of a common synchronization module.
4. The method of claim 1 , wherein the first and second synchronization modules are different.
5. The method of claim 1 , wherein the first and second synchronization modules and the first and second user-created code comprise graphical programs.
6. The method of claim 5 , wherein said associating the first synchronization module with the first user-created code and said associating the second synchronization module with the second user-created code comprises connecting the respective synchronization modules and the respective user-created code in a graphical program.
7. The method of claim 1 , further comprising: providing a library of synchronization modules; and receiving user input selecting the first and second synchronization modules.
8. The method of claim 1 , further comprising: providing a graphical user interface (GUI) for configuring each synchronization module.
9. The method of claim 1 , wherein the first and second synchronization modules comprise first and second synchronization module pairs, comprising processor-side code and PHE-side code.
10. The method of claim 9 , wherein the method further comprises: configuring the test instrument, wherein said configuring comprises configuring the first PHE according to the first hardware description and configuring the second PHE according to the second hardware description, wherein said configuring further comprises storing program instructions corresponding to the processor-side code in one or more memory mediums of the test instrument.
11. The method of claim 1 , wherein the first synchronization module and the second synchronization module provide a first synchronization type for the first and second user-code, wherein the method further comprises: providing a third synchronization module; receiving user input associating the first user-created code with the third synchronization module; providing a fourth synchronization module; receiving user input associating the second user-created code with the fourth synchronization module; wherein said generating the first hardware description is also based on the third synchronization module; wherein said generating the second hardware description is also based on the fourth synchronization module; wherein the third and fourth synchronization modules provide a second synchronization type for the first and second user-code; wherein the first and second synchronization modules and the third and fourth synchronization modules are configured to independently synchronize portions of the first and second user-created code.
12. A non-transitory computer accessible memory medium storing program instructions for customizing a system, wherein the system comprises at least a first programmable hardware element (PHE) and a second PHE, wherein the program instructions are executable to: create a first program for implementation on the first PHE, comprising: receiving user input selecting and inserting a first synchronization module into the first program, wherein the first synchronization module comprises code for implementation on the first PHE, wherein the first synchronization module provides a standard interface for interacting with other code; receiving user input creating first user-created code which performs a first function; receiving user input associating the first synchronization module with the first user-created code in the first program, wherein the first user-code is configured to interact with the first synchronization module using the standard interface; create a second program for implementation on the second PHE, comprising: receiving user input selecting and inserting a second synchronization module, wherein the second synchronization module comprises code for implementation on the second PHE, wherein the second synchronization module provides the standard interface for interacting with other code; receiving user input creating second user-created code which performs a second function; receiving user input associating the second synchronization module with the second user-created code, wherein the second user-created code is configured to interact with the second synchronization module using the standard interface; generate a first hardware description based on the first synchronization module and the associated first user-created code; generate a second hardware description based on the second synchronization module and the associated second user-created code; wherein the first synchronization module in the first hardware description and the second synchronization module in the second hardware description are configured to communicate with each other to synchronize the first user-created code and the second user-created code, and wherein for each of the first and second synchronization modules, the standard interface allows swapping out the synchronization module without requiring modification of the associated user-created code.
13. The non-transitory computer accessible memory medium of claim 12 , wherein the system comprises a first device comprising the first PHE and a second device comprising the second PHE, wherein the first user-created code is implemented on the first device and the second user-created code is implemented on the second device.
14. The non-transitory computer accessible memory medium of claim 12 , wherein the program instructions are further executable to: configure the first PHE according to the first hardware description; and configure the second PHE according to the second hardware description; wherein, during operation, the first PHE and the second PHE operate to communicate with each other to synchronize the first user-created code in the first hardware description and the second user-created code in the second hardware description.
15. The non-transitory computer accessible memory medium of claim 12 , wherein the first user-created code and the second user-created code utilize a plurality of custom triggers, wherein each custom trigger is invoked and received using the first and second synchronization modules.
16. The non-transitory computer accessible memory medium of claim 12 , wherein the first and second synchronization modules are instantiations of a common synchronization module.
17. The non-transitory computer accessible memory medium of claim 12 , wherein the first and second synchronization modules and the first and second user-created code comprise graphical programs.
18. The non-transitory computer accessible memory medium of claim 17 , wherein said associating the first synchronization module with the first user-created code and said associating the second synchronization module with the second user-created code comprises connecting the respective synchronization modules and the respective user-created code in a graphical program.
19. The non-transitory computer accessible memory medium of claim 12 , wherein the program instructions are further executable to: provide a library of synchronization modules; and receive user input selecting the first and second synchronization modules.
20. The non-transitory computer accessible memory medium of claim 12 , wherein the first and second synchronization modules comprise first and second synchronization module pairs, comprising processor-side code and PHE-side code.
21. The non-transitory computer accessible memory medium of claim 12 , wherein the program instructions are further executable to: configure the test instrument, wherein said configuring comprises configuring the first PHE according to the first hardware description and configuring the second PHE according to the second hardware description, wherein said configuring further comprises storing program instructions corresponding to the processor-side code in one or more memory mediums of the test instrument.
22. The non-transitory computer accessible memory medium of claim 12 , wherein the first synchronization module and the second synchronization module provide a first synchronization type for the first and second user-code, wherein the program instructions are further executable to: provide a third synchronization module; receive user input associating the first user-created code with the third synchronization module; provide a fourth synchronization module; receive user input associating the second user-created code with the fourth synchronization module; wherein said generating the first hardware description is also based on the third synchronization module; wherein said generating the second hardware description is also based on the fourth synchronization module; wherein the third and fourth synchronization modules provide a second synchronization type for the first and second user-code; wherein the first and second synchronization modules and the third and fourth synchronization modules are configured to independently synchronize portions of the first and second user-created code.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 19, 2012
August 19, 2014
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