An electronic device comprises an electronic component and an integrated circuit, wherein the integrated circuit is configured to generate a system clock and an external clock having a programmable delay from the system clock, provide the external clock to the electronic component, determine a delay range between system clock and the external clock in which the integrated circuit and the electronic component can communicate, and program the external clock with one of a plurality of predetermined delay values based on the delay range.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic device, comprising: an electronic component; and an integrated circuit configured to generate a system clock, an external clock having a first programmable delay from the system clock, and a feedback clock having a second programmable delay from the system clock, the integrated circuit being further configured to provide the external clock to the electronic component to write data, to provide the feedback clock to read data from the electronic component, determine a lowest passing value and a highest passing value based upon writing and reading data to and from the electronic component, determine a bin based upon the lowest passing value and the highest passing value, and program the first programmable delay of the external clock with one of a plurality of predetermined delay values based on the bin, wherein the first programmable delay is equal to the second programmable delay plus an offset.
2. The electronic device of claim 1 wherein the integrated circuit is further configured to store the predetermined delay values.
3. The electronic device of claim 1 wherein the electronic component comprises at least one memory device.
4. The electronic device of claim 3 wherein the electronic component comprises at least one of SDRAM, Burst NOR, Burst PSRAM, RAM, ROM, EPROM, EEPROM, or VRAM.
5. The electronic device of claim 1 wherein the lowest passing value and the highest passing value are is related to a range of speeds characterizing the integrated circuit and a range of speeds characterizing the electronic component.
6. The electronic device of claim 1 wherein the electronic device comprises a wireless telephone, personal digital assistant, e-mail device, or Web enabled device.
7. A method of calibrating an integrated circuit to an electronic component, the integrated circuit having a system clock, the method comprising: generating an external clock on the integrated circuit, the external clock having a first programmable delay from the system clock; generating a feedback clock on the integrated circuit, the feedback clock having a second programmable delay from the system clock; providing the external clock to write data to the electronic component; providing the feedback clock to read data from the electronic component; determining a lowest passing value and a highest passing value based upon writing and reading data to and from the electronic component; determining a bin based upon the lowest passing value and the highest passing value; and programming the first programmable delay of the external clock with one of a plurality of predetermined delay values based on the bin, wherein the first programmable delay is equal to the second programmable delay plus an offset.
8. The method of claim 7 further comprising storing the predetermined delay values.
9. The method of claim 7 wherein the electronic component comprises at least one memory device.
10. The method of claim 9 wherein the electronic component comprises at least one of SDRAM, Burst NOR, Burst PSRAM, RAM, ROM, EPROM, EEPROM, or VRAM.
11. The method of claim 7 wherein the lowest passing value and the highest passing value are related to a range of speeds characterizing the integrated circuit and a range of speeds characterizing the electronic component.
12. The method of claim 7 wherein the electronic device comprises a wireless telephone, personal digital assistant, e-mail device, or Web enabled device.
13. An electronic device, comprising: an electronic component; and an integrated circuit comprising: means for generating a system clock: means for generating an external clock on the integrated circuit, the external clock having a first programmable delay from the system clock; means for generating a feedback clock on the integrated circuit, the feedback clock having a second programmable delay from the system clock; means for providing the external clock to write data to the electronic component; means for providing the feedback clock to read data from the electronic component; means for determining a lowest passing value and a highest passing value based upon writing and reading data to and from the electronic component; means for determining a bin based upon the lowest passing value and the highest passing value; and means for programming the first programmable delay of the external clock with one of a plurality of predetermined delay values based on the bin, wherein the first programmable delay is equal to the second programmable delay plus an offset.
14. The electronic device of claim 13 further comprising means for storing the predetermined delay values.
15. The electronic device of claim 13 wherein the electronic component comprises at least one memory device.
16. The electronic device of claim 15 wherein the electronic component comprises at least one of SDRAM, Burst NOR, Burst PSRAM, RAM, ROM, EPROM, EEPROM, or VRAM.
17. The electronic device of claim 13 wherein the lowest passing value and the highest passing value are related to a range of speeds characterizing the integrated circuit and a range of speeds characterizing the electronic component.
18. The electronic device of claim 13 wherein the electronic device comprises a wireless telephone, personal digital assistant, e-mail device, or Web enabled device.
19. A non-transitory computer readable medium embodying instructions executable by a processor to perform a method of calibrating an integrated circuit to an electronic component, the integrated circuit including a system clock, an external clock having a first programmable delay from the system clock, and a feedback clock having a second programmable delay from the system clock, the external clock being provided to the electronic component to write data, and the feedback clock to read data from the electronic component, the instructions comprising: at least one instruction for causing the processor to determine a lowest passing value and a highest passing value based upon writing and reading data to and from the electronic component; at least one instruction for determining a bin based upon the lowest passing value and the highest passing value; and at least one instruction for causing the processor to program the first programmable delay of the external clock with one of a plurality of predetermined delay values based on the bin, wherein the first programmable delay is equal to the second programmable delay plus an offset.
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November 4, 2005
August 26, 2014
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