A driver circuit has a pad that may be utilized for programming a core circuit or receiving a data signal. A trace high circuit receives a pad voltage signal from the pad, and outputs a trace high voltage approximating a higher voltage of the pad voltage signal and the power supply voltage. A level shifter and a first inverter output a pull high control signal generated by inverting and level shifting a programming control signal. An ESD blocking circuit selectively blocks the pad voltage signal from reaching the core circuit depending on the pad voltage signal and the level-shifted programming control signal. A pull high circuit receives the pull high control signal and the power supply voltage, and outputs the power supply voltage to the core circuit when the pull high control signal is lower than the power supply voltage.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A driver circuit for driving a core circuit, the driver circuit comprising: a pad for receiving a pad voltage signal; a trace high circuit having a first input terminal coupled to the pad for receiving the pad voltage signal, the trace high circuit further having a second input terminal for receiving a power supply voltage, and an output terminal for outputting a trace high voltage approximating a higher voltage of the pad voltage signal and the power supply voltage; a level shifter having a first input terminal coupled to the output terminal of the trace high circuit for receiving the trace high voltage, a second input terminal for receiving a programming control signal, and an output terminal for outputting a level-shifted programming control signal generated by level shifting the programming control signal according to the trace high voltage; a first inverter having a first input terminal coupled to the trace high circuit for receiving the trace high voltage, a second input terminal coupled to the output terminal of the level shifter, and an output terminal for outputting a pull high control signal generated by inverting the level-shifted programming control signal; an ESD blocking circuit coupled to the level shifter, the pad, and the core circuit, the ESD blocking circuit comprising: a first transistor comprising: an input terminal coupled to the pad for receiving the pad voltage signal; an output terminal; and a control terminal for receiving the level-shifted programming control signal, the control terminal controlling the ESD blocking circuit to block the pad voltage signal from reaching the core circuit when the pad voltage signal is not for programming, and to allow the pad voltage signal to reach the core circuit when the pad voltage signal is for programming; and a pull high circuit coupled to the first inverter and the core circuit for receiving the pull high control signal and the power supply voltage, and outputting the power supply voltage to the core circuit when the pull high control signal is lower than the power supply voltage.
2. The driver circuit of claim 1 , further comprising: an ESD redirection circuit coupled to the pad for receiving the pad voltage signal and an ESD control node for draining ESD charges to ground when voltage of the ESD control node is higher than ground.
3. The driver circuit of claim 2 , further comprising: a resistor having a first terminal coupled to an output terminal of the trace high circuit for receiving the trace high voltage, and a second terminal coupled to a control node; and a gate driven circuit coupled to the control node and the ESD redirection circuit for outputting the voltage of the ESD control node as an inverse of approximately the trace high voltage.
4. The driver circuit of claim 3 , wherein the gate driven circuit comprises a second inverter for receiving the trace high voltage, outputting a low voltage when the trace high voltage is high, and outputting a high voltage when the trace high voltage is low.
5. The driver circuit of claim 2 , further comprising: a control circuit comprising: an input terminal coupled to the trace high circuit for receiving the trace high voltage; an output terminal coupled to the control node; and a control terminal coupled to the ESD control node for shorting the resistor when voltage of the ESD control node is lower than the trace high voltage.
6. The driver circuit of claim 2 , further comprising: a decoupling capacitor having a first terminal coupled to the output terminal of the level shifter and a second terminal coupled to ground.
7. The driver circuit of claim 2 , wherein the ESD blocking circuit further comprises: a second transistor comprising: an input terminal coupled to the output terminal of the first transistor; an output terminal coupled to the core circuit; and a control terminal coupled to the ESD control node for controlling the ESD blocking circuit to block the pad voltage signal from reaching the core circuit when the pad voltage signal is not for programming, and to allow the pad voltage signal to reach the core circuit when the pad voltage signal is for programming.
8. The driver circuit of claim 2 , wherein the trace high circuit comprises: a first transistor comprising: an input terminal coupled to the pad for receiving the pad voltage signal; an output terminal for outputting the trace high voltage; and a control terminal for receiving the power supply voltage for controlling the output terminal to output the pad voltage signal as the trace high voltage when the power supply voltage is lower than the pad voltage signal; a second transistor comprising: an input terminal for receiving the power supply voltage; an output terminal for outputting the trace high voltage; and a control terminal coupled to the pad for receiving the pad voltage signal for controlling the output terminal to output the power supply voltage as the trace high voltage when the pad voltage signal is lower than the power supply voltage.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 7, 2009
August 26, 2014
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