A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming a metal oxide semiconductor field effect transistor, comprising: exposing portions on a substrate having a first dopant polarity adjacent to a gate stack; forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed; annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate, providing sufficient dopant concentration in the substrate to convert the dopant regions from the first dopant polarity to an opposite dopant polarity; removing the dopant layer; depositing a metal containing layer over the gate stack and in contact with the substrate in the exposed portions; annealing the metal containing layer to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions; and removing the metal layer.
2. The method as recited in claim 1 , wherein forming a dopant layer includes forming a layer containing Ge.
3. The method as recited in claim 1 , wherein the substrate includes a III-V material.
4. The method as recited in claim 1 , wherein the substrate includes a p-type substrate and the dopants include n-type dopants and the dopant regions are converted to n-type regions.
5. The method as recited in claim 1 , wherein exposing portions on a substrate adjacent to a gate stack includes patterning a field dielectric to expose the substrate.
6. The method as recited in claim 1 , wherein the substrate includes InGaAs and the metal layer includes Ni and the metal alloy includes a Ni—InGaAs alloy.
7. The method as recited in claim 1 , wherein the dopant layer includes Ge and the step of annealing the dopant layer includes annealing with a rapid thermal anneal having a temperature of about 500 degrees for about 10 minutes.
8. The method as recited in claim 1 , wherein removing the dopant layer includes performing an etch immediately after the step of annealing the dopant layer.
9. A method for forming a metal oxide semiconductor field effect transistor, comprising: exposing portions on a p-type III-V substrate adjacent to a gate stack; forming a dopant layer containing Ge over the gate stack and in contact with the substrate in the portions exposed; annealing the dopant layer to drive Ge dopants into the substrate to form self-aligned dopant regions in the substrate and to convert the p-type substrate to n-type in the dopant regions; removing the dopant layer; depositing a metal containing layer having Ni over the gate stack and in contact with the substrate in the exposed portions; annealing the metal containing layer to drive Ni into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions; and removing the metal containing layer.
10. The method as recited in claim 9 , wherein the substrate includes GaAs.
11. The method as recited in claim 9 , wherein exposing portions on a substrate adjacent to a gate stack includes patterning a field dielectric to expose the substrate.
12. The method as recited in claim 9 , wherein the substrate includes InGaAs and the self-aligned contact regions include a Ni—InGaAs alloy.
13. The method as recited in claim 9 , wherein annealing the dopant layer includes annealing with a rapid thermal anneal having a temperature of about 500 degrees for about 10 minutes.
14. The method as recited in claim 9 , wherein removing the dopant layer includes performing an etch immediately after the step of annealing the dopant layer.
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September 5, 2012
September 2, 2014
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