A memory device, comprising a first control input port, a second control input port, a third control input port, a data input port, a data output port, an internal memory and control circuitry. The control circuitry is responsive to a control signal on the first control input port to capture command and address information via the data input port. When the command is a read command, the control circuitry is further responsive to a read control signal on the second control input port to transfer data associated with the address information from the internal memory onto the data output port. When the command is a write command, the control circuitry is responsive to a write control signal on the third control input port to write data captured via the data input port into the internal memory at a location associated with the address information.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for execution by a memory controller connectable to a chain of serially-connected memory devices, the method comprising: asserting a read data control signal on a first port to delimit a read data packet request (RDPR) destined for a first target memory device of the chain; asserting a write data control signal on a second port different from the first port to delimit a write data packet (WDP) destined for a second target memory device of the chain; the RDPR and the WDP being of different lengths.
2. The method of claim 1 , further comprising: placing data to be written to the second target memory device onto an data output port while asserting the write data control signal.
3. The method of claim 2 , further comprising: asserting a command and address control signal to delimit a first command and address packet (CAP) destined for the first target memory device, the first CAP alerting the first target memory device to the RDPR; asserting the command and address control signal to delimit a second command and address packet (CAP) destined for the second target memory device, the second CAP alerting the second target memory device to the WDP.
4. The method of claim 3 , wherein the first CAP is formulated to contain at least one of a Burst Data Read Start command, a Burst Data Read command and a Read Status Register command.
5. The method of claim 3 , wherein the second CAP is formulated to contain at least one of a Burst Data Load Start command, a Burst Data Load command and a Write Link Configuration Register command.
6. The method of claim 3 , further comprising: placing command and address information destined for the first target memory device onto the data output port while asserting the command and address signal control signal to delimit the first CAP; and placing command and address information destined for the second target memory device onto the data output port while asserting the command and address signal control signal to delimit the second CAP.
7. The method of claim 6 , wherein the command and address information destined for the first target memory device comprises an identifier of the first target memory device and wherein the command and address information destined for the second target memory device comprise an identifier of the second target memory device.
8. The method of claim 1 , further comprising de-asserting the read data control signal to suspend the RDPR and re-asserting the read data control signal to resume the RDPR.
9. The method of claim 8 , wherein the write data control signal is asserted while the RDP is suspended.
10. The method of claim 1 , further comprising de-asserting the write data control signal to suspend the WDP and re-asserting the write data control signal to resume the WDP.
11. The method of claim 10 , wherein the read data control signal is asserted while the WDP is suspended.
12. The method of claim 1 , further comprising producing at least one clock signal, wherein the read data control signal and the write data control signal are referenced at transition edges of the at least one clock signal.
13. The method of claim 1 , further comprising: detecting assertion of a command and address control signal received from the last memory device of the chain at a control input port of the memory controller; receiving data from the last memory device at a data input port of the memory controller while the received command and address control signal is asserted; the received data comprising data read form the first target memory device in response to the RDPR.
14. A method for execution by a memory controller connectable to a chain of serially-connected memory devices, the method comprising: asserting a read data control signal to delimit a read data packet request (RDPR) destined for a first target memory device of the chain; asserting a write data control signal to delimit a write data packet (WDP) destined for a second target memory device of the chain; wherein the RDPR and the WDP are time interleaved with respect to one another.
15. The method of claim 14 , further comprising: placing data to be written to the second target memory device onto an data output port while asserting the write data control signal.
16. The method of claim 15 , further comprising; asserting a command and address control signal to delimit a first command and address packet (CAP) destined for the first target memory device, the first CAP alerting the first target memory device to the RDPR; asserting the command and address control signal to delimit a second command and address packet (CAP) destined for the second target memory device, the second CAP alerting the second target memory device to the WDP.
17. The method of claim 16 , wherein: the first CAP conveys at least one of a Burst Data Read Start command, a Burst Data Read command and a Read Status Register command; and the second CAP conveys at least one of a Burst Data Load Start command, a Burst Data Load command and a Write Link Configuration Register command.
18. The method of claim 16 , further comprising: placing command and address information destined for the first target memory device onto the data output port while asserting the command and address signal control signal to delimit the first CAP; and placing command and address information destined for the second target memory device onto the data output port while asserting the command and address signal control signal to delimit the second CAP.
19. The method of claim 18 , wherein the command and address information destined for the first target memory device comprises an identifier of the first target memory device and wherein the command and address information destined for the second target memory device comprise an identifier of the second target memory device.
20. The method of claim 14 , further comprising de-asserting the read data control signal to suspend the RDPR and re-asserting the read data control signal to resume the RDPR.
21. The method of claim 20 , wherein the write data control signal is asserted while the RDP is suspended.
22. The method of claim 14 , further comprising de-asserting the write data control signal to suspend the WDP and re-asserting the write data control signal to resume the WDP.
23. The method of claim 22 , wherein the read data control signal is asserted while the WDP is suspended.
24. The method of claim 14 , further comprising producing at least one free-running clock signal, wherein the read data control signal and the write data control signal are referenced at transition edges of the at least one free-running clock signal.
25. The method of claim 14 , further comprising: detecting assertion of a command and address control signal received from the last memory device of the chain at a control input port of the memory controller; receiving data from the last memory device at a data input port of the memory controller while the received command and address control signal is asserted; the received data comprising data read form the first target memory device in response to the RDPR.
26. A memory device, comprising: a first control input port; a second control input port; a third control input port; a data input port; a data output port; an internal memory; control circuitry responsive to a control signal on the first control input port to capture command and address information via the data input port; wherein when the command is a read command, the control circuitry is further responsive to a read control signal on the second control input port to transfer data associated with the address information from the internal memory onto the data output port; and wherein when the command is a write command, the control circuitry is further responsive to a write control signal on the third control input port to write data captured via the data input port into the internal memory at a location associated with the address information.
27. The memory device of claim 26 , wherein the command and address information comprises a command and address packet (CAP) having a stream of consecutive bytes that include device identifier bytes, command bytes and/or memory address bytes.
28. The memory device of claim 26 , wherein the command bytes convey information pertaining to the command to be executed by a destination memory device, and wherein the number of bytes in the CAP depends on the command.
29. The memory device of claim 26 , wherein the control circuitry is responsive to the write control signal or the read control signal if the write command or the read command is destined for the memory device.
30. The memory device of claim 26 , wherein the control circuitry is further configured to extract a device identifier from the control signal on the first control input port.
31. The memory device of claim 30 , wherein the control circuitry is responsive to the write control signal or the read control signal if the extracted device identifier matches an assigned identifier of the memory device.
32. The memory device of claim 26 , forming part of a chain with at least one other memory device, wherein the control circuitry is configured to forward the control signal on the first control input port to a next device of the chain.
33. The memory device of claim 32 , wherein when the command is a read command, the control circuitry is further configured to transfer the signal on the third control input port to the next device of the chain.
34. The memory device of claim 33 , wherein the signal on the third control input port delimits a write data packet (WDP) destined for another memory device of the chain.
35. The memory device of claim 32 , wherein when the command is a read command, the control circuitry is further configured to transfer the read control signal to the next device of the chain.
36. The memory device of claim 32 , wherein when the command is a write command, the control circuitry is further configured to transfer the signal on the second control input port to the next device of the chain.
37. The memory device of claim 36 , wherein the signal on the third control input port delimits a read data packet request (RDPR) destined for another memory device of the chain.
38. The memory device of claim 37 , wherein when the command is a write command, the control circuitry is further configured to suspend transferring the write control signal to the next device of the chain.
39. The memory device of claim 26 , wherein when the command is a read command, the control circuitry is further responsive to de-assertion of the read control signal to suspend transferring data from the internal memory onto the data output port.
40. The memory device of claim 39 , wherein during the time when the control circuitry has suspended transferring data from the internal memory onto the data output port, the control circuitry is further configured to transfer data from the data input port to the data output port and to transfer the signals on the first, second and third control inputs to the next device of the chain.
41. The memory device of claim 40 , wherein when the command is a read command, the control circuitry is further responsive to re-assertion of the read control signal to resume transferring data from the internal memory onto the data output port.
42. The memory device of claim 26 , wherein when the command is a write command, the control circuitry is further responsive to de-assertion of the write control signal to suspend writing data captured via the data input port to the internal memory.
43. The memory device of claim 42 , wherein during the time when the control circuitry has suspended writing data captured via the data input port to the internal memory, the control circuitry is further configured to transfer the captured data from the data input port to the data output port and to transfer the signals on the first, second and third control inputs to the next device of the chain.
44. The memory device of claim 43 , wherein when the command is a write command, the control circuitry is further responsive to re-assertion of the write control signal to resume writing data captured from the data input port to the internal memory.
45. The memory device of claim 26 , wherein the data input port and the data output port each include a plurality of pins for transporting data in parallel to and from the memory device.
46. The memory device of claim 26 , wherein the read control signal and the write control signal are referenced at transition edges of at least one clock signal received from a memory controller.
47. The memory device of claim 26 , wherein the command is at least one of a Burst Data Load Start command, a Burst Data Load command, a Write Link Configuration Register command, a Burst Data Read Start command, a Burst Data Read command and a Read Status Register command.
48. The memory device of claim 26 , wherein the internal memory comprises solid state memory.
49. The memory device of claim 26 , wherein the internal memory comprises semiconductor memory.
50. The memory device of claim 26 , wherein the internal memory comprises at least one of volatile memory, non-volatile memory and a combination of volatile and non-volatile memory.
51. The memory device of claim 26 , wherein the internal memory comprises flash memory.
52. The memory device of claim 26 , comprising at least one of NAND Flash EEPROM, NOR Flash EEPROM, AND Flash EEPROM, DiNOR Flash EEPROM, Serial Flash EEPROM, DRAM, SRAM, ROM, EPROM, FRAM, MRAM and PCRAM.
53. A memory system, comprising a memory controller connected to a chain of memory devices according to claim 26 .
54. A memory device connectable to a next device of a chain, comprising: an input/output interface; an internal memory; control circuitry; wherein the control circuitry is configured to recognize a command received via the interface and destined for the memory device; wherein when the command is a read command destined for the memory device, the control circuitry is further configured to: respond to a read control signal received via the interface by sending data from the internal memory towards the next device via the interface; and transfer a write control signal received via the interface towards the next device via the interface; wherein when the command is a write command destined for the memory device, the control circuitry is further configured to: respond to the write control signal by writing data captured from the interface to the internal memory; and transfer the read control signal received via the interface towards the next device via the interface.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 21, 2012
September 2, 2014
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.