Routing centric design closure

1. A method of placing and routing circuit components comprising: dividing a layout area of an integrated circuit (IC) design into an array of tiles, each tile having a plurality of edges that are common to adjoining tiles; placing of circuit components into the layout area of the IC design such that each tile including a plurality of circuit components, the placing of circuit components being performed for primarily routability without resort to a timing model, routability being measured by congestion of wiring nets at the tile edges; performing a virtual timing operation of the IC design with a virtual timing model assuming ideal buffering is done to test the placement of circuit components; performing a wire synthesis operation of the IC design for layer assignment, buffering and timing optimization while minimizing degradation in routability; and performing a plurality of timing optimizations of the IC design while minimizing degradation in routability; moving circuit components during the plurality of timing optimizations such that a disruptiveness of moving circuit components varies from more disruptive in early timing optimizations to less disruptive in later timing optimizations; wherein the placing of circuit components starts good routability and the following timing optimization steps maintain the good routability; and wherein the method is performed by one or more computing devices.

2. The method of claim 1 further comprising adding one or more buffers after one of the plurality of timing optimizations.

3. The method of claim 1 wherein the layout area includes a plurality of metallization layers for routing wires and wherein the layer assignment of the wire synthesis includes routing at least one wire from a first metallization layer to a second metallization layer to relieve congestion or reduce timing delays on the first metallization layer.

4. The method of claim 1 wherein performing a virtual timing operation includes performing a layer assignment wherein the layer assignment includes routing at least one wire from a first metallization layer to a second metallization layer to relieve congestion or reduce timing delays on the first metallization layer.

5. The method of claim 1 wherein the virtual timing model includes any linear delay model that calculates a delay between any two connection points in the IC design assuming that buffers or inverters are inserted into the IC design optimally.

6. The method of claim 1 wherein the virtual timing operation includes a wiring model in combination with the virtual timing model such that the wiring model determines the point to point wiring topology for each wiring net of the IC design and the virtual timing model calculates the post-buffering timing delay for each point to point wiring net.

7. The method of claim 1 wherein if the virtual timing operation determines that the timing of the IC design is acceptable, then the method directly proceeds to wire synthesis while when the timing of the IC design is not acceptable in virtual timing, then further comprising incrementally moving the circuit components to improve the timing of the design.

8. The method of claim 7 wherein wire synthesis includes layer assignment, buffering, gate sizing and other optimization techniques.

9. The method of claim 1 wherein the plurality of timing optimizations include gate sizing, threshold voltage assignment and optimization, logic optimizations, layer assignment and cell movement.

10. A computer program product for placing and routing circuit components, the computer program product comprising: a non-transitory computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising: computer readable program code configured to divide a layout area of an integrated circuit (IC) design into an array of tiles, each tile having a plurality of edges that are common to adjoining tiles; computer readable program code configured to place circuit components into the layout area of the IC design such that each tile including a plurality of circuit components, the placement of circuit components being performed for primarily routability without resort to a timing model, routability being measured by congestion of wiring nets at the tile edges; computer readable program code configured to perform a virtual timing operation of the IC design with a virtual timing model assuming ideal buffering is done to test the placement of circuit components; computer readable program code configured to perform a wire synthesis operation of the IC design for layer assignment, buffering and timing optimization while minimizing degradation in routability; and computer readable program code configured to perform a plurality of timing optimizations of the IC design while minimizing degradation in routability; computer readable program code configured to move circuit components during the plurality of timing optimizations such that a disruptiveness of moving circuit components varies from more disruptive in early timing optimizations to less disruptive in later timing optimizations; and wherein the placing of circuit components starts good routability and the following timing optimization steps maintain the good routability.

11. The computer program product of claim 10 further comprising computer readable program code configured to add one or more buffers after one of the plurality of timing optimizations.

12. The computer program product of claim 10 wherein the layout area includes a plurality of metallization layers for routing wires and wherein the layer assignment of the wire synthesis includes computer readable program code configured to route at least one wire from a first metallization layer to a second metallization layer to relieve congestion or reduce timing delays on the first metallization layer.

13. The computer program product of claim 10 wherein computer readable program code configured to perform a virtual timing operation includes computer readable program code configured to perform a layer assignment wherein the layer assignment includes routing at least one wire from a first metallization layer to a second metallization layer to relieve congestion or reduce timing delays on the first metallization layer.

14. The computer program product of claim 10 wherein the virtual timing model includes any linear delay model that calculates a delay between any two connection points in the IC design assuming that buffers or inverters are inserted into the IC design optimally.

15. The computer program product of claim 10 wherein the virtual timing operation includes a wiring model in combination with the virtual timing model such that the wiring model determines the point to point wiring topology for each wiring net of the IC design and the virtual timing model calculates the post-buffering timing delay for each point to point wiring net.

16. The computer program product of claim 10 wherein when the virtual timing operation determines that the timing of the IC design is acceptable, then the computer program product directly proceeds to computer readable program code configured to perform wire synthesis while when the timing of the IC design is not acceptable in virtual timing, then further comprising computer readable program code configured to incrementally move the circuit components to improve the timing of the design.

17. The computer program product of claim 16 wherein wire synthesis includes layer assignment, buffering, gate sizing and other optimization techniques.

18. The computer program product of claim 10 wherein the plurality of timing optimizations include gate sizing, threshold voltage assignment and optimization, logic optimizations, layer assignment and cell movement.