Silicon carbide semiconductor device

1. A silicon carbide semiconductor device comprising: an insulation film, and a silicon carbide layer having a surface covered with said insulation film, said surface including a first region, said first region having a first plane orientation at least partially, said first plane orientation being any of a (0-33-8) plane, (30-3-8) plane, (-330-8) plane, (03-3-8) plane, (−303-8) plane, and (3-30-8) plane, wherein said surface of said silicon carbide layer further includes a second region, said second region having a second plane orientation differing from said first plane orientation, at least partially, said second plane orientation is any of the (0-33-8) plane, (30-3-8) plane, (-330-8) plane, (03-3-8) plane, (-303-8) plane, and (3-30-8) plane.

2. The silicon carbide semiconductor device according to claim 1 , wherein said surface of said silicon carbide layer further includes third to sixth regions, said third to sixth regions, at least partially, having third to sixth plane orientations respectively, said first to sixth plane orientations differing from each other, and each of said first to sixth plane orientations is any of the (0-33-8) plane, (30-3-8) plane, (-330-8) plane, (03-3-8) plane, (-303-8) plane, and (3-30-8) plane.

3. The silicon carbide semiconductor device according to claim 1 , wherein an interface between said silicon carbide layer and said insulation film has an interface state density less than 5×10 11 cm −2 eV −1 .

4. The silicon carbide semiconductor device according to claim 1 , wherein said silicon carbide semiconductor device has an S value less than or equal to 200 mV/decade.

5. The silicon carbide semiconductor device according to claim 1 , further comprising a gate electrode provided on said insulation film.

6. The silicon carbide semiconductor device according to claim 5 , wherein said gate electrode constitutes a trench gate structure.

7. The silicon carbide semiconductor device according to claim 5 , wherein said gate electrode constitutes a planar gate structure.

8. The silicon carbide semiconductor device according to claim 1 , wherein said silicon carbide layer has channel mobility higher than or equal to 70 cm 2 /Vs at room temperature on said surface.

9. The silicon carbide semiconductor device according to claim 8 , wherein said silicon carbide layer has an impurity concentration greater than or equal to 1×10 17 cm −3 on said surface.

10. The silicon carbide semiconductor device according to claim 9 , wherein said silicon carbide semiconductor device has a threshold value greater than or equal to 4V.

11. The silicon carbide semiconductor device according to claim 1 , wherein said silicon carbide layer has channel mobility higher than or equal to 100 cm 2 /Vs at room temperature on said surface.

12. The silicon carbide semiconductor device according to claim 11 , wherein said silicon carbide layer has an impurity concentration greater than or equal to 2×10 16 cm −3 on said surface.

13. The silicon carbide semiconductor device according to claim 12 , wherein said silicon carbide semiconductor device has a threshold value greater than or equal to 2.5V.

14. A silicon carbide semiconductor device comprising: an insulation film, and a silicon carbide layer having a surface covered with said insulation film, said surface including a first region, said first region having a first plane orientation at least partially, an off orientation of said first plane orientation to a {0001} plane being within a range of ±5° to a <1-100> direction, an off angle of said first plane orientation to a {03-38} plane in the <1-100> direction being greater than or equal to −3° and less than or equal to 3°, and an inclination of said first plane orientation to a (000-1) plane being less than 90°, wherein said surface of said silicon carbide layer further includes a second region, said second region having a second plane orientation differing from said first plane orientation at least partially, an off orientation of said second plane orientation to the {0001} plane being within the range of ±5° to the <1-100> direction, an off angle of said second plane orientation to the {03-38} plane in the <1-100> direction being greater than or equal to −3° and less than or equal to 3°, and an inclination of said second plane orientation to the (000-1) plane being less than 90°.

15. The silicon carbide semiconductor device according to claim 14 , wherein said surface of said silicon carbide layer further includes third to sixth regions, said third to sixth regions, at least partially, having third to sixth plane orientations respectively, said first to sixth plane orientations differing from each other, each off orientation of said first to sixth plane orientations to the {0001} plane being within the range of ±5° to the <1-100> direction, each off angle of each of said first to sixth plane orientations to the {03-38} plane in the <1-100> direction being greater than or equal to −3° and less than or equal to 3°, and each inclination of each of said first to sixth plane orientations to the (000-1) plane being less than 90°.

16. The silicon carbide semiconductor device according to claim 14 , wherein an interface between said silicon carbide layer and said insulation film has an interface state density less than 5×10 11 cm −2 eV −1 .

17. The silicon carbide semiconductor device according to claim 14 , wherein said silicon carbide semiconductor device has an S value less than or equal to 200 mV/decade.

18. The silicon carbide semiconductor device according to claim 14 , further comprising a gate electrode provided on said insulation film.

19. The silicon carbide semiconductor device according to claim 18 , wherein said gate electrode constitutes a trench gate structure.

20. The silicon carbide semiconductor device according to claim 18 , wherein said gate electrode constitutes a planar gate structure.

21. The silicon carbide semiconductor device according to claim 14 , wherein said silicon carbide layer has channel mobility higher than or equal to 70 cm 2 /Vs at room temperature on said surface.

22. The silicon carbide semiconductor device according to claim 21 , wherein said silicon carbide layer has an impurity concentration greater than or equal to 1×10 17 cm −3 on said surface.

23. The silicon carbide semiconductor device according to claim 22 , wherein said silicon carbide semiconductor device has a threshold value greater than or equal to 4V.

24. The silicon carbide semiconductor device according to claim 14 , wherein said silicon carbide layer has channel mobility higher than or equal to 100 cm 2 /Vs at room temperature on said surface.

25. The silicon carbide semiconductor device according to claim 24 , wherein said silicon carbide layer has an impurity concentration greater than or equal to 2×10 16 cm −3 on said surface.

26. The silicon carbide semiconductor device according to claim 25 , wherein said silicon carbide semiconductor device has a threshold value greater than or equal to 2.5V.