A method of operating a controller for controlling the programming of a NAND memory chip is shown. The NAND memory chip has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum erasable unit. The method comprising storing in a temporary storage a first plurality of groups of data, wherein each of the groups of data is to be stored in a block of the NAND memory chip. Each group of data is indexed to the block with which it is to be stored. Finally, the groups of data associated with the same block are programmed into the same block in the same programming operation.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of operating a controller for controlling the programming of a NAND memory chip, wherein said NAND memory chip has a plurality of blocks with each block having a plurality of groups of storage, wherein the amount of storage in each block is the minimum erasable unit, wherein said method comprising: storing a plurality of groups of data in a plurality of blocks of a temporary storage, wherein at least two of the groups of data in one of the plurality of blocks of the temporary storage are to be stored in different blocks of the plurality of blocks of said NAND memory chip, and wherein at least two of the groups of data in different ones of the plurality of blocks of the temporary storage are to be stored in the same block of the plurality of blocks of said NAND memory chip; indexing, in an index table, each of the groups of data in the blocks of temporary storage to a group of storage in the block in the NAND memory chip where it is to be stored; identifying all of the plurality of groups of data stored in the temporary storage which are to be stored in the same block of the plurality of blocks of said NAND memory chip; writing all the identified a plurality of the groups of data from the temporary storage along with data stored in the same block into an erased block of the NAND memory chip different from the same block of the NAND memory chip; deleting the groups of data from the temporary storage that were written to the erased block; and deleting, from the index table, the index for the groups of data deleted from the temporary storage.
2. The method of claim 1 wherein each of the plurality of groups of storage is a page.
3. The method of claim 1 wherein said indexing step comprises: creating a table of the logic address to the physical address of the groups of data written into the temporary storage.
4. The method of claim 1 wherein said writing step writes all of the groups of data from the temporary storage.
5. The method of claim 4 wherein said deleting the groups of data deletes all of the groups of data from the temporary storage.
6. The method of claim 5 wherein said deleting from the index table step deletes all of the index.
7. The method of claim 1 wherein said deleting the groups of data step further comprises: deleting only the groups of data that were written and performing a garbage collection step to consolidate the remaining groups of data in the temporary storage.
8. The method of claim 7 wherein said deleting from the index table further comprises: deleting only the index for the groups of data written and performing a garbage collection step to consolidate the remaining indices in the index table.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 1, 2010
September 16, 2014
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