Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A bonded structure comprising a vertical stack containing, from bottom to top, at least: a first semiconductor substrate; a first interconnect-level structure; a first planar dielectric layer; a layer complementarily filled with metal semiconductor alloy portions and vertical stacks of dielectric material portions, each of said vertical stacks of dielectric material portions including a first dielectric material portion and a second dielectric material portion that contact each other within a same interface plane that is common across all of said vertical stacks; a second planar dielectric layer; a second interconnect-level structure; and a second semiconductor substrate, wherein an entire top surface of one of said metal semiconductor alloy portions is in physical contact with a dielectric surface of said second planar dielectric layer, an entire bottom surface of said one of said metal semiconductor alloy portions is in physical contact with a dielectric surface of said first planar dielectric layer, and entire sidewall surfaces of said one of said metal semiconductor alloy portions are in physical contact with surfaces of said vertical stacks of dielectric material portions.
2. The bonded structure of claim 1 , wherein said metal semiconductor alloy portions are comprised of an alloy of at least one metal selected from transition metals, Lanthanides, and Actinides, and at least one semiconductor element selected from Si and Ge.
3. The bonded structure of claim 2 , wherein said metal semiconductor alloy portions are comprised of a metal silicide, a metal germanide, or a metal germanosilicide.
4. The bonded structure of claim 3 , wherein said at least one metal is nickel or a metallic alloy including at least 30% of nickel in atomic percentage.
5. The bonded structure of claim 1 , wherein an entire interface between said first planar dielectric layer and said complementarily filled layer is planar.
6. The bonded structure of claim 5 , wherein an entire interface between said second planar dielectric layer and said complementarily filled layer is planar.
7. The bonded structure of claim 1 , wherein said first interconnect-level structure comprises first conductive wiring structures and at least one first dielectric material layer, and said second interconnect-level structure comprises second conductive wiring structures and at least one second dielectric material layer.
8. The bonded structure of claim 7 , wherein said first interconnect-level structure is more proximal to said same interface plane than said first semiconductor substrate, and said second interconnect-level structure is more proximal to said same interface plane than said second semiconductor substrate.
9. The bonded structure of claim 7 , wherein at least one of said first conductive wiring structures and said second conductive wiring structures contacts a top surface or a bottom surface of another of said metal semiconductor alloy portions.
10. The bonded structure of claim 7 , further comprising: at least two through-substrate via structures that extend through said second semiconductor substrate and said second interconnect-level structure; and at least one metal line contacting said at least two through-substrate via structures.
11. The bonded structure of claim 10 , wherein one of said at least two through-substrate via structures contacts one of said second conductive wiring structures.
12. The bonded structure of claim 10 , wherein one of said at least two through-substrate via structures contacts one of said metal semiconductor alloy portions.
13. The bonded structure of claim 10 , wherein one of said at least two through-substrate via structures contacts one of said first conductive wiring structures.
14. The bonded structure of claim 1 , further comprising a third substrate vertically contacting one of said first and second substrates, wherein said second substrate further includes third dielectric material portions and said third substrate includes fourth dielectric material portions, each of said fourth dielectric material portions contacts a surface of one of said third dielectric material portions at a second interface plane between said second and third substrates, said third dielectric material portions and said fourth dielectric material portions laterally contact second metal semiconductor alloy portions, and each of said second metal semiconductor alloy portions extends across said second interface into said second substrate and said third substrate.
15. The bonded structure of claim 1 , wherein said metal semiconductor alloy portions include at least one metal semiconductor alloy portion that is not in direct contact with any conductive structure embedded in at least one of said first interconnect-level structure, said first planar dielectric layer, said second planar dielectric layer, and said second interconnect-level structure.
16. The bonded structure of claim 1 , wherein each of said metal semiconductor alloy portions is not in direct contact with any conductive structure embedded in at least one of said first interconnect-level structure, said first planar dielectric layer, said second planar dielectric layer, and said second interconnect-level structure.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 12, 2010
September 23, 2014
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