A circuit and a method for implementing Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT) are provided. The method includes: determining the number m of iterations, depth d1 of the first and second Random Access Memories (RAMs), depth d2 of a Read Only Memory (ROM); storing the first and second n/2 parts of the input data to be Transformed into the second and first RAMs respectively; performing the iterative butterfly operations m times; in the first iteration, reading the first and second RAMs in a reverse bit order, writing the results of the even-numbered butterfly operations into the first RAM, writing the results of the odd-numbered butterfly operations into the second RAM; during the second to the (m−1)th iterations, reading the first and second RAMs in a normal bit order, wherein the way to write back to the RAM is the same as that of the first time; in the m-th iteration, reading the first and second RAMs in a normal bit order, wherein the location in the RAM to be written back is the same as the location for reading.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A circuit for implementing Fast Fourier Transform/Inverse Fast Fourier Transform (FFT/IFFT), comprising: a first multiplexer, a second multiplexer, a first Random Access Memory (RAM), a second RAM, a Read Only Memory (ROM), a third multiplexer, a fourth multiplexer, a complex multiplier, a first complex adder and a second complex adder; the circuit further comprising two data output ends and two data input ends, wherein the two data output ends are output ends of the third and fourth multiplexers respectively or output ends of the first and second RAMs respectively; two input ends of the first multiplexer are connected with one of the data input ends of the circuit and an output end of the first complex adder respectively; two input ends of the second multiplexer are connected with the other data input end of the circuit and an output end of the second complex adder respectively; an output end of the first multiplexer is connected with a data input end of the first RAM; an output end of the second multiplexer is connected with a data input end of the second RAM; input signals of two input ends of the third multiplexer are the output signal of the output end of the first RAM and 0.5 times the output signal of the output end of the first RAM respectively; input signals of two input ends of the fourth multiplexer are the output signal of the output end of the second RAM and 0.5 times of the output signal of the output end of the second RAM respectively; two input ends of the complex multiplier are connected with the output end of the third multiplexer and an output end of ROM respectively; input signals of the two input ends of the first complex adder are the output signal of the output end of the fourth multiplexer and −1 times the output signal of an output end of the complex multiplier respectively; two input ends of the second complex adder are connected with the output end of the fourth multiplexer and the output end of the complex multiplier respectively.
2. The circuit according to claim 1 , wherein the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer all are 2-to-1 multiplexers.
3. A circuit for implementing FFT/IFFT, comprising: a first multiplexer, a second multiplexer, a first RAM, a second RAM, an ROM, a third multiplexer, a fourth multiplexer, a complex multiplier, a first complex adder and a second complex adder; the circuit further comprising two data output ends and two data input ends, wherein the two data output ends are output ends of the third and fourth multiplexers respectively or output ends of the first and second RAMs respectively; two input ends of the first multiplexer are connected with one of the data input ends of the circuit and the output end of the third multiplexer respectively; two input ends of the second multiplexer are connected with the other data input end of the circuit and the output end of the fourth multiplexer respectively; an output end of the first multiplexer is connected with an input end of the first RAM; an output end of the second multiplexer is connected with an input end of the second RAM; two input ends of the complex multiplier are connected with the output end of the first RAM and an output end of ROM respectively; input signals of two input ends of the first complex adder are output signal of the output end of the second RAM and −1 times the output signal of an output end of the complex multiplier respectively; two input ends of the second complex adder are connected with an output end of the complex multiplier and the output end of the second RAM respectively; input signals of two input ends of the third multiplexer are output signal of output end of the first complex adder and 0.5 times the output signal of the output end of the first complex adder respectively; input signals of two input ends of the fourth multiplexer are output signal of an output end of the second complex adder and 0.5 times the output signal of the output end of the second complex adder respectively.
4. The circuit according to claim 3 , wherein the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer all are 2-to-1 multiplexers.
5. A method for implementing FFT/IFFT using a circuit, comprising: A: determining a number m of iterations, depth d 1 of a first and second RAMs in the circuit, and depth d 2 of a ROM in the circuit according to a length n of input data of FFT/IFFT; B: storing first n/2 part of the input data of FFT/IFFT into the second RAM and last n/2 part into the first RAM; C: performing iterative butterfly operations for m times, wherein in the first iteration, when reading the first and second RAMs, adopting a reverse bit order to read, writing the iteration results back to the first and second RAMs, wherein the results of the even-numbered butterfly operations are written into the first RAM, the results of the odd-numbered butterfly operations are written into the second RAM; in the second to the (m−1)th iterations, when reading the first and second RAMs, adopting a normal bit order to read, wherein the way to write back to the first and second RAMs is the same as that of the first iteration; in the m-th iteration, when reading the first and second RAMs, adopting a normal bit order to read, wherein the locations in the first and second RAMs to be written back are the same as the locations for reading.
6. The method according to claim 5 , wherein in Step A, the number m of iterations is the minimal integer greater than or equal to log 2 (n); the depth d 1 of the first and second RAMs is equal to n; the depth d 2 of ROM is equal to n/2 or n*m/2.
7. The method according to claim 6 , wherein in Step B, the first and last n/2 parts of the input data of FFT/IFFT are written into a high areas of the second and first RAMs respectively; or the first and last n/2 parts are written into a low areas of the second and first RAMs respectively; or the first n/2 part is written into the high area/low area of the second RAM, and correspondingly, the last n/2 part is written into the low area/high area of the first RAM.
8. The method according to claim 7 , wherein in Step C, for all the iterations in the first to the (m−1)th iterations, if the data of an iteration is read out from the high area of the second/first RAM, the result of this iteration is written into the low area of the corresponding RAM; if the data of an iteration is read out from the low area of the second/first RAM, the result of this iteration is written into the high area of the corresponding RAM.
9. The method according to claim 5 , wherein in Step B, the first and last n/2 parts of the input data of FFT/IFFT are written into a high areas of the second and first RAMs respectively; or the first and last n/2 parts are written into a low areas of the second and first RAMs respectively; or the first n/2 part is written into the high area/low area of the second RAM, and correspondingly, the last n/2 part is written into the low area/high area of the first RAM.
10. The method according to claim 9 , wherein in Step C, for all the iterations in the first to the (m−1)th iterations, if the data of an iteration is read out from the high area of the second/first RAM, the result of this iteration is written into the low area of the corresponding RAM; if the data of an iteration is read out from the low area of the second/first RAM, the result of this iteration is written into the high area of the corresponding RAM.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 11, 2009
September 23, 2014
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.