A semiconductor device includes: a foundation layer that is provided on a substrate and is electrically conductive; a nickel layer provided on the foundation layer; and a solder provided on the nickel layer, the nickel layer having a first region on a side of the foundation layer and a second region on a side of the solder, the second region being harder than the first region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a foundation layer that is provided on a substrate and is electrically conductive; a nickel layer provided on the foundation layer; and a solder provided on the nickel layer, the nickel layer having a first region on a side of the foundation layer and a second region on a side of the solder, the second region being harder than the first region.
2. The semiconductor device as claimed in claim 1 , wherein: hardness of the first region is 150 Hv or more and less than 500 Hv; and hardness of the second region is 500 Hv or more to 1000 Hv or less.
3. The semiconductor device as claimed in claim 2 , wherein difference of hardness between the first region and the second region is 100 Hv or more.
4. The semiconductor device as claimed in claim 1 , wherein the solder is a solder ball.
5. The semiconductor device as claimed in claim 1 , wherein the hardness of the nickel layer changes in stages from the first region to the second region.
6. The semiconductor device as claimed in claim 1 , wherein the hardness of the nickel layer continuously changes from the first region to the second region.
7. The semiconductor device as claimed in claim 1 , wherein a thickness of the first region and the second region is 0.1 μm or more to 5 μm or less.
8. The semiconductor device as claimed in claim 1 , wherein the foundation layer includes at least one of gold, copper and aluminum.
9. The semiconductor device as claimed in claim 1 further comprising a cover layer located between the nickel layer and the solder.
10. The semiconductor device as claimed in claim 9 , wherein the cover layer covers an upper face and a side face of the nickel layer.
11. The semiconductor device as claimed in claim 9 , wherein the cover layer is gold or silver.
12. The semiconductor device as claimed in claim 9 , wherein: concavity and convexity is formed on a surface of the nickel layer; and concavity and convexity is formed on a surface of the cover layer according to the concavity and convexity of the nickel layer.
13. A method for manufacturing a semiconductor device comprising: forming a foundation layer on a substrate; providing a nickel layer, of which upper face side is harder than lower face side, on the foundation layer; and providing a solder on the nickel layer.
14. The method as claimed in claim 13 , wherein the nickel layer is formed by an electroless plating method in which a concentration of phosphorous in a growing of the upper face side of the nickel layer is lower than that in a growing of the lower face side of the nickel layer.
15. The method as claimed in claim 13 , wherein the nickel layer is formed by a heat treatment in which a temperature of the upper face side of the nickel layer is higher than that of the lower face side of the nickel layer, after forming the nickel layer.
16. The method as claimed in claim 15 , wherein the heat treatment is a laser annealing.
17. The method as claimed in claim 13 , wherein the nickel layer is formed by an electroless plating method in which a temperature of the upper face side of the nickel layer is higher than that of the lower face side of the nickel layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 28, 2012
September 30, 2014
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