Prefetch request circuit

1. A prefetch request circuit provided in a processor device, the processor device having hierarchized two or more storage areas, the processor device being able to prefetch data of address to be used between appropriate storage areas among the two or more storage areas, when executing respective instruction flows obtained by multi-flow expansion for one instruction at a time of decoding of the instruction, the prefetch request circuit comprising: a latch unit to hold, when a state in which the respective instruction flows to access the storage area are executed with a maximum specifiable data transfer volume is specified, the state during a time period of the multi-flow expansion; and a prefetch request signal output unit to output a prefetch request signal to request the prefetch every time when the instruction flow is executed, based on an output signal of the latch unit and a signal indicating an execution timing of the respective instruction flows.

2. The prefetch request circuit according to claim 1 , wherein the prefetch request circuit is provided in a reservation station executing the instruction flow.

3. A prefetch request circuit in a processor apparatus having a main memory, a secondary cache and a primary data cache, performing multi-flow expansion for one instruction to obtain a plurality of instruction flows at a time of decoding the instruction, executing the respective instruction flows, and being able to prefetch data of address to be used from the main memory to the secondary cache at a time of memory access to the primary data cache, the prefetch request circuit comprising: a latch circuit unit to hold, when a state in which the respective instruction flows corresponding to a memory copy instruction specifying data copy or move between memory addresses and operation are executed with a maximum specifiable data transfer volume is specified, the state during a time period of the multi-flow expansion; and an AND circuit unit to perform AND operation between an output signal of the latch unit and a signal indicating an execution timing of the respective instruction flows and to output the AND operation result as a prefetch request signal every time when the respective instruction flows are issued.

4. The prefetch request circuit according to claim 3 , wherein the prefetch request circuit is provided in a reservation station executing the instruction flow.