Obfuscating program by scattering sequential instructions into memory regions such that jumps occur with steps of both signs in equal frequency

1. A data processing device, comprising: a functional unit for executing instructions from a memory, an address output for supplying target addresses of instructions to the memory; and a program flow control unit configured to determine the target addresses for supply to the address output, the program flow control unit being configured to introduce address steps of position dependent size and/or direction between target addresses of instructions at logically successive positions in the program, at least part of the address steps not corresponding to instruction size, wherein a sequence of successive original instruction addresses is assigned to a set of respective target addresses, with successive address steps between the target addresses to which the successive original instruction addresses are mapped, the target addresses of the set lying in a plurality of non-overlapping address ranges, the mapping filling at least half of each of the ranges with instructions, the successive address steps comprising first address steps within at least a first one of the ranges and, between said first address steps, second address steps within at least a second one of the ranges; and wherein the program flow control unit is configured to generate the address steps of mutually opposite sign between target addresses of logically successive instructions with equal frequency.

2. A data processing device according claim 1 , wherein assignment of original instruction addresses to target addresses corresponds to mapping successive original instruction addresses to successive locations in a path along points in an n-dimensional array, where n is greater than one, the path wandering in all dimensions of the array, and mapping locations along respective rows, groups of rows, or row parts of said array to respective ones of the ranges, the path consisting of steps between adjacent locations in the array, visiting at least half the points of each row of the array.

3. A data processing device according claim 1 , wherein the sequence of instructions is a proper subset of a super-sequence comprising further sequences of instruction addresses that are mapped to target addresses under control of the secret information, at least a mapping within said ranges is controlled by a part of the secret information that does not affect mapping of the further sequences.

4. A data processing device according claim 1 , wherein the sequence of instructions is a proper subset of a super-sequence comprising further sequences of instruction addresses that are mapped to target addresses in further address ranges, the non-overlapping address ranges being mutually separated by said further address ranges intervening between the non-overlapping address ranges.

5. A data processing device according claim 1 , configured to determine target addresses based on a hierarchy with successive levels of cells, each cell corresponding to a respective set of ranges, cells at successively lower levels corresponding to sub-sets of ranges that are sub-sets of the sets of cells at higher levels, the cells in the hierarchy being associated with indices, the device comprising: a program counter; a look up circuit providing sub-division information that defines the sets of ranges as a function of values of the indices and path information that defines respective ones of target addresses to which respective values of the indices map within the set of ranges of a lowest level cell, the lookup circuit having inputs coupled to the program counter for receiving index values; and a combining circuit configured to combine sub-division information from different levels that has been accessed under control of the program counter to define the set of ranges of the lowest level cell for said at least one of the original instruction addresses and to combine the accessed path information to select the target address for the at least one original instruction address within the set of ranges defined by combining the accessed sub-division information.

6. A data processing device according claim 1 , wherein a look-up circuit is configured to provide alternatives for the path information, the alternatives defining a plurality of mutually distinct alternatively relations between the respective ones of target addresses and the values of the indices, the combining circuit being configured to combine respective accessed sub-division information obtained for mutually different ones of the original instruction addresses respectively and to use the combined respective accessed sub-division information to control selection of respective different ones of the alternatives for determining the target addresses for the mutually different ones of the original instruction addresses.

7. A method of executing a computer program of instructions at logically successive positions, the method comprising: determining target addresses of the instructions, with address steps of position dependent size and/or direction between target addresses of instructions from logically successive positions in the program, at least part of the address steps not corresponding to instruction size; using the target addresses to retrieve the instructions from a memory; and executing the retrieved instructions, wherein instructions from a sequence of logically successive original instruction addresses are retrieved from a set of respective target addresses, with successive address steps between the target addresses from which the logically successive original instruction addresses are retrieved, the target addresses of the respective set lying in a plurality of non-overlapping address ranges, at least half of each of the ranges being filled with instructions from the sequence, the successive address steps comprising first address steps within at least a first one of the ranges and, between said first address steps, second address steps within at least a second one of the ranges; wherein pseudo randomly selected address steps are used; and wherein address steps of mutually opposite sign are used with equal frequency.

8. A method according claim 1 , wherein the mapping of original instruction addresses to target addresses corresponds to mapping successive original instruction addresses to successive locations in a path along points in an n-dimensional array, where n is greater than one, the path wandering in all dimensions of the array, and mapping locations along respective rows, groups of rows, or row parts of said array to respective ones of the ranges, the path consisting of steps between adjacent locations in the array, visiting at least half the points of each row of the array.