A device for controlling frequency synchronization includes a processor for controlling a phase-controlled clock signal to achieve phase-locking with a reference clock signal, and for controlling a frequency-controlled clock signal so as to achieve frequency-locking with the reference clock signal. The processor is also configured to monitor a deviation between the frequency and phase-controlled clock signals, detect a change of circumstances such as temperature changes causing frequency drifting of the frequency-controlled clock signal, and replace or correct the frequency-controlled clock signal with, or on the basis of, the phase-controlled clock signal when both the monitored deviation and the detected change of circumstances show correlation confirming frequency drift of the frequency-controlled clock signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A control device for controlling frequency synchronization, the control device comprising a processor configured to: form phase-error indicators on the basis of first values of reception moments of timing messages transmitted in accordance with a reference clock signal, the first values of the reception moments being expressed as time values based on a phase-controlled clock signal, form frequency-error indicators on the basis of second values of the reception moments of the timing messages, the second values of the reception moments being expressed as time values based on a frequency-controlled clock signal, control the phase-controlled clock signal with the phase-error indicators so as to achieve phase-locking between the reference clock signal and the phase-controlled clock signal, control the frequency-controlled clock signal with the frequency-error indicators so as to achieve frequency-locking between the reference clock signal and the frequency-controlled clock signal, monitor a deviation between the frequency-controlled clock signal and the phase-controlled clock signal, detect, on the basis of a quantity measured from a system generating the frequency-controlled clock signal, a change of circumstances tending to cause frequency drifting of the frequency-controlled clock signal, and replace or correct the frequency-controlled clock signal with or on the basis of the phase-controlled clock signal in response to a situation in which both the monitored deviation between the frequency- and phase-controlled clock signals and the detected change of circumstances show correlation confirming frequency drift of the frequency-controlled clock signal.
2. The control device according to claim 1 , wherein the processor is further configured to determine, on the basis of the measured quantity, an estimate for a maximum rate of the frequency drifting of the frequency-controlled clock signal that is in concordance with the change of the circumstances, and to limit the rate of frequency change of the frequency-controlled clock signal in accordance with the estimate when correcting the frequency-controlled clock signal on the basis of the phase-controlled clock signal.
3. The control device according to claim 1 , wherein the processor is configured, for the purpose of forming each of the phase-error indicators, to calculate a difference between the first value of the reception moment of the respective timing message and a time-stamp value related to this timing message.
4. The control device according to claim 1 , wherein the processor is configured, for the purpose of forming each of the phase-error indicators, to calculate a difference between the first value of the reception moment of the respective timing message and an ideal reception moment of this timing message, the ideal reception moments of the timing messages being spaced at equal intervals so that a difference between any two successive ideal reception moments is constant.
5. The control device according to claim 1 , wherein the processor is configured, for the purpose of forming each of the frequency-error indicators, to calculate a first quantity that is a difference between the second values of the reception moments of such two timing messages which have experienced a substantially similar transfer delay, calculate a second quantity that is a difference of time-stamp values related to these two timing messages, and calculate a difference between the first and second quantities.
6. The control device according to claim 5 , wherein the processor is configured to select the two timing messages to be such timing messages which have, on the basis of the second values of their reception moments, smallest estimated transfer delays.
7. The control device according to claim 1 , wherein the processor is configured, for the purpose of forming each of the frequency-error indicators, to calculate a first quantity that is a difference between the second values of the reception moments of such two timing messages which have experienced a substantially similar transfer delay, calculate a second quantity that is a difference of ideal reception moments of these two timing messages, and calculate a difference between the first and second quantities, the ideal reception moments of the timing messages being spaced at equal intervals so that a difference between any two successive ideal reception moments is constant.
8. The control device according to claim 1 , wherein the quantity measured from a system generating the frequency-controlled clock signal is indicative of at least an internal and/or ambient temperature of an oscillator of the system generating the frequency-controlled clock signal.
9. The control device according to claim 8 , wherein the processor is configured, for the purpose of correcting the frequency-controlled clock signal, to change the frequency of the frequency-controlled clock signal towards the frequency of the phase-controlled clock signal with a pre-stored value chosen on the basis of a change in the measured internal and/or ambient temperature of the oscillator.
10. The control device according to claim 1 , wherein the quantity measured from a system generating the frequency-controlled clock signal is indicative of at least one of the following: changes of supply voltage of an oscillator of the system generating the frequency-controlled clock signal, changes of current consumption of the oscillator.
11. The control device according to claim 1 , wherein the processor is configured, for the purpose of monitoring the deviation between the frequency-controlled clock signal and the phase-controlled clock signal, to calculate a difference between a first control signal determining the frequency of the phase-controlled clock signal and a second control signal determining the frequency of the frequency-controlled clock signal.
12. The control device according to claim 1 , wherein the processor is configured, for the purpose of monitoring the deviation between the frequency-controlled clock signal and the phase-controlled clock signal, to compare the phase of the phase-controlled clock signal to the phase of the frequency-controlled clock signal.
13. A network element comprising: at least one ingress port for receiving timing messages transmitted in accordance with a reference clock signal, and a controllable clock signal generator for producing a first controllable clock signal and a second controllable clock signal, the network element being arranged to operate in accordance with the second controllable clock signal, wherein network element further comprises a control device for controlling the clock signal generator so that the first controllable clock signal is a phase-controlled clock signal and the second controllable clock signal is a frequency-controlled clock signal, the control device comprising a processor configured to: form phase-error indicators on the basis of first values of reception moments of the timing messages, the first values of the reception moments being expressed as time values based on the phase-controlled clock signal, form frequency-error indicators on the basis of second values of the reception moments of the timing messages, the second values of the reception moments being expressed as time values based on the frequency-controlled clock signal, control the phase-controlled clock signal with the phase-error indicators so as to achieve phase-locking between the reference clock signal and the phase-controlled clock signal, control the frequency-controlled clock signal with the frequency-error indicators so as to achieve frequency-locking between the reference clock signal and the frequency-controlled clock signal, monitor a deviation between the frequency-controlled clock signal and the phase-controlled clock signal, detect, on the basis of a quantity measured from the clock signal generator generating the frequency-controlled clock signal, a change of circumstances tending to cause frequency drifting of the frequency-controlled clock signal, and replace or correct the frequency-controlled clock signal with or on the basis of the phase-controlled clock signal in response to a situation in which both the monitored deviation between the frequency- and phase-controlled clock signals and the detected change of circumstances show correlation confirming frequency drift of the frequency-controlled clock signal.
14. The network element according to claim 13 , wherein the controllable clock signal generator comprises a crystal oscillator and a first numerically controllable frequency divider for producing the phase-controlled clock signal from an output signal of the crystal oscillator and a second numerically controllable frequency divider for producing the frequency-controlled clock signal from the output signal of the crystal oscillator.
15. The network element according to claim 13 , wherein the network element is at least one of the following: an Internet Protocol (“IP”) router, an Ethernet switch, a MultiProtocol Label Switching (“MPLS”) switch.
16. A method for controlling frequency synchronization, the method comprising: forming phase-error indicators on the basis of first values of reception moments of timing messages transmitted in accordance with a reference clock signal, the first values of the reception moments being expressed as time values based on a phase-controlled clock signal, controlling the phase-controlled clock signal with the phase-error indicators so as to achieve phase-locking between the reference clock signal and the phase-controlled clock signal, forming frequency-error indicators on the basis of second values of the reception moments of the timing messages, the second values of the reception moments being expressed as time values based on a frequency-controlled clock signal, controlling the frequency-controlled clock signal with the frequency-error indicators so as to achieve frequency-locking between the reference clock signal and the frequency-controlled clock signal, monitoring a deviation between the frequency-controlled clock signal and the phase-controlled clock signal, detecting, on the basis of a quantity measured from a system generating the frequency-controlled clock signal, a change of circumstances tending to cause frequency drifting of the frequency-controlled clock signal, and replacing or correcting the frequency-controlled clock signal with or on the basis of the phase-controlled clock signal in response to a situation in which both the monitored deviation between the frequency- and phase-controlled clock signals and the detected change of circumstances show correlation confirming frequency drift of the frequency-controlled clock signal.
17. The method according to claim 16 , wherein the method further comprises determining, on the basis of the measured quantity, an estimate for a maximum rate of the frequency drifting of the frequency-controlled clock signal that is in concordance with the change of the circumstances, and limiting the rate of frequency change of the frequency-controlled clock signal in accordance with the estimate when correcting the frequency-controlled clock signal on the basis of the phase-controlled clock signal.
18. The method according to claim 16 , wherein the method comprises, for the purpose of forming each of the phase-error indicators, calculating a difference between the first value of the reception moment of the respective timing message and a time-stamp value related to this timing message.
19. The method according to claim 16 , wherein the method comprises, for the purpose of forming each of the phase-error indicators, calculating a difference between the first value of the reception moment of the respective timing message and an ideal reception moment of this timing message, the ideal reception moments of the timing messages being spaced at equal intervals so that a difference between any two successive ideal reception moments is constant.
20. The method according to claim 16 , wherein the method comprises, for the purpose of forming each of the frequency-error indicators, calculating a first quantity that is a difference between the second values of the reception moments of such two timing messages which have experienced a substantially similar transfer delay, calculating a second quantity that is a difference of time-stamp values related to these two timing messages, and calculating a difference between the first and second quantities.
21. The method according to claim 20 , wherein the method comprises selecting the two timing messages to be such timing messages which have, on the basis of the second values of their reception moments, smallest estimated transfer delays.
22. The method according to claim 16 , wherein the method comprises, for the purpose of forming each of the frequency-error indicators, calculating a first quantity that is a difference between the second values of the reception moments of such two timing messages which have experienced a substantially similar transfer delay, calculating a second quantity that is a difference of ideal reception moments of these two timing messages, and calculating a difference between the first and second quantities, the ideal reception moments of the timing messages being spaced at equal intervals so that a difference between any two successive ideal reception moments is constant.
23. The method according to claim 16 , wherein the quantity measured from a system generating the frequency-controlled clock signal is indicative of at least an internal and/or ambient temperature of an oscillator of the system generating the frequency-controlled clock signal.
24. The method according to claim 23 , wherein the method comprises, for the purpose of correcting the frequency-controlled clock signal, changing the frequency of the frequency-controlled clock signal towards the frequency of the phase-controlled clock signal with a pre-stored value chosen on the basis of a change in the measured internal and/or ambient temperature of the oscillator.
25. The method according to claim 16 , wherein the quantity measured from a system generating the frequency-controlled clock signal is indicative of at least one of the following: changes of supply voltage of an oscillator of the system generating the frequency-controlled clock signal, changes of current consumption of the oscillator.
26. The method according to claim 16 , wherein the method comprises, for the purpose of monitoring the deviation between the frequency-controlled clock signal and the phase-controlled clock signal, calculating a difference between a first control signal determining the frequency of the phase-controlled clock signal and a second control signal determining the frequency of the frequency-controlled clock signal.
27. The method according to claim 16 , wherein the method comprises, for the purpose of monitoring the deviation between the frequency-controlled clock signal and the phase-controlled clock signal, comparing the phase of the phase-controlled clock signal to the phase of the frequency-controlled clock signal.
28. A non-transitory computer readable medium encoded with a computer program for controlling frequency synchronization, the computer program comprising computer executable instructions for controlling a programmable processor to: form phase-error indicators on the basis of first values of reception moments of timing messages transmitted in accordance with a reference clock signal, the first values of the reception moments being expressed as time values based on a phase-controlled clock signal, form frequency-error indicators on the basis of second values of the reception moments of the timing messages, the second values of the reception moments being expressed as time values based on a frequency-controlled clock signal, control the phase-controlled clock signal with the phase-error indicators so as to achieve phase-locking between the reference clock signal and the phase-controlled clock signal, control the frequency-controlled clock signal with the frequency-error indicators so as to achieve frequency-locking between the reference clock signal and the frequency-controlled clock signal, monitor a deviation between the frequency-controlled clock signal and the phase-controlled clock signal, detect, on the basis of a quantity measured from a system generating the frequency-controlled clock signal, a change of circumstances tending to cause frequency drifting of the frequency-controlled clock signal, and replace or correct the frequency-controlled clock signal with or on the basis of the phase-controlled clock signal in response to a situation in which both the monitored deviation between the frequency- and phase-controlled clock signals and the detected change of circumstances show correlation confirming frequency drift of the frequency-controlled clock signal.
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March 16, 2012
October 7, 2014
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