A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising a semiconductor chip having: a semiconductor substrate; a multilayered interconnect having a bottom surface contacting said semiconductor substrate and an uppermost surface opposite to the bottom surface; an inductor embedded within said multilayered interconnect and spaced apart from the bottom and uppermost surfaces; a plurality of first pads respectively physically contacting external electrode terminals on said uppermost surface of said multilayered interconnect in a region around the inductor on at least three sides thereof in a plan view, the first pads being in direct physical contact with the respective external electrode terminals; and a circuit forming region provided right under said first pads, wherein an area of said uppermost surface of said multilayered interconnect overlapping said inductor does not include any pads for physically contacting external electrode terminals, and wherein an area of an upper side of said semiconductor substrate overlapping said inductor does not include any circuit elements.
2. The semiconductor device according to claim 1 , wherein said first pads are provided in a plurality of regions closer than said inductor to side surfaces of said semiconductor chip in a plan view.
3. The semiconductor device according to claim 1 , wherein said first pads are regularly arranged in a plan view, except the area that overlaps said inductor.
4. The semiconductor device according to claim 3 , wherein said first pads are arranged in a square pattern in a plan view, in a region other than the area that overlaps said inductor.
5. The semiconductor device according to claim 1 , further comprising: bumps provided on said first pads, wherein said bumps are provided in a region, which does not overlap said inductor in a plan view.
6. The semiconductor device according to claim 5 , further comprising: a mounting substrate having conductive second pads, wherein said semiconductor chip is mounted by connecting said bumps to said second pads, wherein said second pads are provided in a region, which does not overlap said inductor of said semiconductor chip in a plan view.
7. The semiconductor device according to claim 6 , wherein said mounting substrate has a first interconnect which is provided in the same layer as said second pads, and said first interconnect is provided in a region, which does not overlap said inductor of said semiconductor chip in a plan view.
8. The semiconductor device according to claim 7 , wherein said mounting substrate has a second interconnect located one layer under said first interconnect, and said second interconnect is provided in a region, which does not overlap said inductor of said semiconductor chip in a plan view.
9. The semiconductor device according to claim 8 , wherein said mounting substrate has a third interconnect located one layer under said second interconnect, and said third interconnect is provided in a region, which does not overlap said inductor of said semiconductor chip in a plan view.
10. The semiconductor device according to claim 6 , wherein all the interconnects of said mounting substrate are provided in a region, which does not overlap said inductor of said semiconductor chip in a plan view.
11. The semiconductor device according to claim 1 , wherein said inductor is a coil in said interconnect layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 2, 2007
October 14, 2014
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.