Patentable/Patents/US-8860651
US-8860651

Display panel and gate driver therein

PublishedOctober 14, 2014
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A gate driver includes cascade-connected driving stages. Each of the driving stages includes a first shift register circuit and a second shift register circuit. The first shift register circuit is configured for outputting a present stage driving signal and a next stage driving signal. The second shift register circuit is electrically coupled to the first shift register circuit and configured for outputting a present stage gate signal, a first next stage gate signal, and a second next stage gate signal. Furthermore, a display panel is also provided herein.

Patent Claims
18 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A gate driver comprising a plurality of cascade-connected driving stages, each of the driving stages comprising: a first shift register circuit comprising: a first input unit for outputting a first control signal according to a previous stage driving signal; a first drive output unit for outputting a present stage driving signal according to the first control signal and a first driving clock signal; and a second drive output unit for outputting a next stage driving signal according to the first control signal and a second driving clock signal; and a second shift register circuit electrically coupled to the first shift register circuit, the second shift register circuit comprising: a second input unit for outputting a second control signal according to the previous stage driving signal; a first output unit for outputting a present stage gate signal according to the second control signal and a first gate clock signal; a second output unit for outputting a first next stage gate signal according to the second control signal and a second gate clock signal; and a third output unit for outputting a second next stage gate signal according to the second control signal and a third gate clock signal, wherein the first driving clock signal and the second driving clock signal have a high voltage level of a power voltage and a low voltage level of a first reference voltage, and the first gate clock signal, the second gate clock signal and the third gate clock signal have a high voltage level of the power voltage and a low voltage level of a second reference voltage, wherein the second reference voltage is greater than the first reference voltage.

2

2. The gate driver as claimed in claim 1 , wherein the first shift register circuit further comprises: a pull-down control unit controlled with the first control signal to output a pull-down control signal according to the first driving clock signal or a power voltage.

3

3. The gate driver as claimed in claim 2 , wherein the first shift register circuit further comprises: a first pull-down unit for electrically coupling a present stage driving signal output terminal and a next stage driving signal output terminal to the first reference voltage according to the pull-down control signal.

4

4. The gate driver as claimed in claim 3 , wherein the first pull-down unit further comprises: a first switch for electrically coupling a first control signal output terminal to the present stage driving signal output terminal according to the pull-down control signal; a second switch for electrically coupling the first control signal output terminal to the next stage driving signal output terminal according to the pull-down control signal; and a third switch for electrically coupling the next stage driving signal output terminal to the first reference voltage according to the pull-down control signal.

5

5. The gate driver as claimed in claim 4 , wherein the first pull-down unit further comprises: a fourth switch for electrically coupling the present stage driving signal output terminal to the first reference voltage according to the pull-down control signal.

6

6. The gate driver as claimed in claim 3 , wherein the first pull-down unit further comprises: a first switch for electrically coupling a first control signal output terminal to the first reference voltage according to the pull-down control signal; a second switch for electrically coupling the present stage driving signal output terminal to the first reference voltage according to the pull-down control signal; and a third switch for electrically coupling the next stage driving signal output terminal to the first reference voltage according to the pull-down control signal.

7

7. The gate driver as claimed in claim 1 , wherein the second shift register circuit further comprises: a second pull-down unit for electrically coupling a present stage gate signal output terminal, a first next stage gate signal output terminal and a second next stage gate signal output terminal to the second reference voltage according to the pull-down control signal; wherein the second reference voltage is greater than the first reference voltage.

8

8. The gate driver as claimed in claim 7 , wherein the second pull-down unit further comprises: a first switch for electrically coupling the present stage gate signal output terminal to the second reference voltage according to the pull-down control signal; a second switch for electrically coupling the first next stage gate signal output terminal to the second reference voltage according to the pull-down control signal; a third switch for electrically coupling the second next stage gate signal output terminal to the second reference voltage according to the pull-down control signal; and a fourth switch for electrically coupling a second control signal output terminal to a third reference voltage according to the pull-down control signal.

9

9. The gate driver as claimed in claim 1 , wherein the first input unit further comprises: a first switch for electrically coupling a power voltage to a first control signal output terminal according to the previous stage driving signal; and a second switch for electrically coupling a third reference voltage to the first control signal output terminal according to a first next stage driving signal; the second input unit further comprises: a third switch for electrically coupling the power voltage to a second control signal output terminal according to the previous stage driving signal; and a fourth switch for electrically coupling the third reference voltage to the second control signal output terminal according to the first next stage driving signal; wherein the second reference voltage is greater than the third reference voltage, and the third reference voltage is greater than the first reference voltage.

10

10. The gate driver as claimed in claim 1 , wherein the first drive output unit further comprises a first switch for transmitting the first driving clock signal as the present stage driving signal according to the first control signal; and the second drive output unit further comprises a second switch for transmitting the second driving clock signal as the next stage driving signal according to the first control signal.

11

11. The gate driver as claimed in claim 1 , wherein the first output unit further comprises a first switch for transmitting the first gate clock signal as the present stage gate signal according to the second control signal; the second output unit further comprises a second switch for transmitting the second gate clock signal as the first next stage gate signal according to the second control signal; and the third output unit further comprises a third switch for transmitting the third gate clock signal as the second next stage gate signal according to the second control signal.

12

12. The gate driver as claimed in claim 1 , wherein the first driving clock signal and the second driving clock signal have a phase difference of one-quarter period, the first gate clock signal, the second gate clock signal and the third gate clock signal have phases that are different from one another, and the first driving clock signal and the first gate clock signal have a same phase.

13

13. A display panel comprising: a plurality of data lines; a plurality of gate lines interlacing with the data lines; and a gate driver coupled to the gate lines and configured for outputting a plurality of gate signals sequentially to the gate lines, wherein the gate driver comprises a plurality of cascade-connected driving stages, and each of the driving stages comprises: a first input unit for electrically coupling a power voltage to a first control signal output terminal according to a previous stage driving signal or for electrically coupling a first reference voltage to the first control signal output terminal according to a next stage driving signal; a first switch for outputting a first driving clock signal as a present stage driving signal according to a voltage level of the first control signal output terminal; a second switch for outputting a second driving clock signal as a second next stage driving signal according to the voltage level of the first control signal output terminal; a second input unit for electrically coupling the power voltage to a second control signal output terminal according to the previous stage driving signal or for electrically coupling the first reference voltage to the second control signal output terminal according to the next stage driving signal; a third switch for outputting a first gate clock signal as a present stage gate signal according to a voltage level of the second control signal output terminal; a first pull-down unit for electrically coupling a present stage driving signal output terminal and a second next stage driving signal output terminal to a second reference voltage according to a pull-down control signal; and a second pull-down unit for electrically coupling a present stage gate signal output terminal, a first next stage gate signal output terminal and a second next stage gate signal output terminal to a third reference voltage according to the pull-down control signal; wherein the third reference voltage is greater than the first reference voltage, and the first reference voltage is greater than the second reference voltage.

14

14. The display panel as claimed in claim 13 , wherein each of the driving stages further comprises: a fourth switch for outputting a second gate clock signal as a first next stage gate signal according to the voltage level of the second control signal output terminal; and a fifth switch for outputting a third gate clock signal as a second next stage gate signal according to the voltage level of the second control signal output terminal.

15

15. The display panel as claimed in claim 14 , wherein the first pull-down unit further comprises: a sixth switch for electrically coupling the first control signal output terminal to the present stage driving signal output terminal according to the pull-down control signal; a seventh switch for electrically coupling the first control signal output terminal to the second next stage driving signal output terminal according to the pull-down control signal; and an eighth switch for electrically coupling the second next stage driving signal output terminal to the second reference voltage according to the pull-down control signal.

16

16. The display panel as claimed in claim 14 , wherein the first pull-down unit further comprises: a sixth switch for electrically coupling the first control signal output terminal to the second reference voltage according to the pull-down control signal; a seventh switch for electrically coupling the present stage driving signal output terminal to the second reference voltage according to the pull-down control signal; and an eighth switch for electrically coupling the second next stage driving signal output terminal to the second reference voltage according to the pull-down control signal.

17

17. The display panel as claimed in claim 14 , wherein the second pull-down unit further comprises: a sixth switch for electrically coupling the present stage gate signal output terminal to the third reference voltage according to the pull-down control signal; a seventh switch for electrically coupling the first next stage gate signal output terminal to the third reference voltage according to the pull-down control signal; an eighth switch for electrically coupling the second next stage gate signal output terminal to the third reference voltage according to the pull-down control signal; and a ninth switch for electrically coupling the second control signal output terminal to the first reference voltage according to the pull-down control signal.

18

18. The display panel as claimed in claim 14 , wherein the first driving clock signal and the second driving clock signal have a high voltage level of the power voltage and a low voltage level of the second reference voltage, and the first gate clock signal, the second gate clock signal and the third gate clock signal have a high voltage level of the power voltage and a low voltage level of the third reference voltage.

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Patent Metadata

Filing Date

April 27, 2012

Publication Date

October 14, 2014

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Cite as: Patentable. “Display panel and gate driver therein” (US-8860651). https://patentable.app/patents/US-8860651

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