Patentable/Patents/US-8866147
US-8866147

Method and system for a GaN self-aligned vertical MESFET

PublishedOctober 21, 2014
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.

Patent Claims
7 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A semiconductor structure comprising: a III-nitride substrate; a drift region coupled to the III-nitride substrate along a growth direction; a channel region coupled to the drift region, wherein the channel region is defined by channel sidewalls disposed substantially along the growth direction and a top surface extending laterally between the channel sidewalls; a gate region comprising a Schottky metal structure and disposed laterally with respect to the channel region; and a dielectric layer overlying a portion of the top surface of the channel region and the gate region.

2

2. The semiconductor structure of claim 1 wherein the Schottky metal structure is not present on the top surface of the channel region.

3

3. The semiconductor structure of claim 1 wherein: the drift region comprises a first III-nitride epitaxial layer of a first conductivity type; and the channel region comprises a second III-nitride epitaxial layer of the first conductivity type coupled to the first III-nitride epitaxial layer.

4

4. The semiconductor structure of claim 1 wherein the channel sidewall is angled with respect to the growth direction to form a reentrant profile.

5

5. The semiconductor structure of claim 1 wherein the Schottky metal structure comprises at least one of nickel, platinum, palladium, or gold.

6

6. The semiconductor structure of claim 1 wherein the drift region has a thickness between 1 μm and 100 μm.

7

7. The semiconductor structure of claim 1 wherein a width of the channel region measured along a direction orthogonal to the growth direction is less than 5 μm.

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Patent Metadata

Filing Date

December 22, 2011

Publication Date

October 21, 2014

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