A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A pixel cell comprising: a photodiode (PD) region in a semiconductor for generating charge, and a storage node (SN) region in the semiconductor, selectively connected to the PD region, for holding a charge transferred from the PD region, wherein a top portion of the PD region is implanted adjacent to a side of the SN region, a bottom portion of the PD region is extended under the SN region, the bottom portion of the PD region is effective in reducing parasitic charges diffusing to the SN region, a P-well region is implanted under the SN region, and a high dose p-type isolation region is implanted in the P-well region, and is disposed under the SN region for reducing parasitic charges diffusing to the SN region, wherein the top portion of the PD region is smaller in width than the bottom portion of the PD region, and a side of the top portion of the PD region is connected to the bottom portion of the PD region by an angular section extending under the SN region.
2. The pixel cell of claim 1 wherein a storage gate (SG) of a transistor is disposed above the SN region, and the SG is immersed within a first dielectric layer; a metallic layer is disposed above the SG and the SN region, and the metallic layer is immersed within a second dielectric layer; and the metallic layer is extended in a depth dimension, into the first dielectric layer, for reducing parasitic charges diffusing to the SN region.
3. The pixel cell of claim 1 wherein a metallic layer disposed above the SN region is coated with an anti-reflective layer for reducing parasitic charges diffusing to the SN region.
4. The pixel cell of claim 3 wherein the metallic layer is coated with a titanium nitride (TiN) layer.
5. The pixel cell of claim 1 wherein a dielectric layer disposed above the SN region includes hydrogen infused silicon nitride (Si3N4) for reducing parasitic charges diffusing to the SN region.
6. The pixel cell of claim 1 wherein a voltage is applied to the PD region, after the PD region is finished transferring the charge from the PD region to the SN region.
7. A global shutter pixel cell comprising: serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor, wherein the SG is immersed within a first dielectric layer, the serially connected transistors coupled between a voltage supply and a floating diffusion (FD) region, a terminal of a photodiode (PD) connected between respective terminals of the AB and the SG transistors, and a terminal of a storage node (SN) diode connected between respective terminals of the SG and the TX transistors, wherein a region of the PD is extended about a region of the SN diode, so that the region of the PD shields the region of the SN diode from stray photons, the region of the PD is extended below and under the region of the SN diode, and a metallic layer, disposed above the SN diode, is extended downwardly toward the SN diode, so that the metallic layer shields the SN diode from stray photons, wherein the metallic layer is immersed within a second dielectric layer and wherein the metallic layer extends into the first dielectric layer in a depth dimension.
8. The global shutter pixel cell of claim 7 wherein a top surface of the metallic layer is coated with an anti-reflective layer.
9. The global shutter pixel cell of claim 7 wherein the first dielectric layer, disposed above the SN diode, includes material for forming a partially non-transparent dielectric layer, so that the first dielectric layer shields the SN diode from stray photons.
10. The global shutter pixel of claim 9 wherein the material for forming the partially non-transparent dielectric layer is hydrogen infused silicon nitride (Si3N4).
11. The global shutter pixel cell of claim 7 wherein the voltage supply is connected to the terminal of the PD, by activating the AB transistor, after the SN includes charge transferred from the PD.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 30, 2011
November 4, 2014
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