An e-fuse array circuit includes a high voltage pumping unit configured to generate a high voltage by pumping a power source voltage, a negative voltage pumping unit configured to generate a negative voltage by pumping a ground voltage, a program/read line supplied with the high voltage when a program operation is activated, a read voltage, which is lower than the high voltage, when a read operation is activated, or the negative voltage when deactivated, a row line supplied with the ground voltage when the row line is activated or the negative voltage when the row line is deactivated, an e-fuse device supplied with voltage of the program/read line, a switch device controlled by the row line and configured to electrically connect the e-fuse device with a column line, and a column circuit configured to supply the negative voltage to the column line when the column line is activated.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An e-fuse array circuit, comprising: a high voltage pumping unit configured to generate a high voltage by pumping a power source voltage; a negative voltage pumping unit configured to generate a negative voltage by pumping a ground voltage; a program/read line supplied with the high voltage when a program operation is activated, a read voltage, which is lower than the high voltage, when a read operation is activated, or the negative voltage when deactivated; a row line supplied with the ground voltage when the row line is activated or the negative voltage when the row line is deactivated; an e-fuse device supplied with voltage of the program/read line; a switch device controlled by the row line and configured to electrically connect the e-fuse device with a column line; and a column circuit configured to supply the negative voltage to the column line when the column line is activated.
2. The e-fuse array circuit of claim 1 , wherein the read voltage is divided from the power source voltage.
3. The e-fuse array circuit of claim 1 , wherein the read voltage is the power source voltage.
4. The e-fuse array circuit of claim 1 , wherein the column circuit supplies the ground voltage to the column line when the column line is deactivated.
5. The e-fuse array circuit of claim 1 , wherein the high voltage has a level of approximately 3.5 to 4.5V, the read voltage has a level of approximately 1.5 to 2.5V, and the negative voltage has a level of approximately −1.5 to −2.5V.
6. An e-fuse array circuit, comprising: a high voltage pumping unit configured to generate a high voltage by pumping a power source voltage; a negative voltage pumping unit configured to generate a negative voltage by pumping a ground voltage; a plurality of memory cells arranged in a plurality of rows and a plurality of columns, and each configured to comprise an e-fuse device and a switch device; a plurality of program/read lines configured to control the e-fuse devices of the plurality of memory cells; a plurality of row lines configured to control the switch devices of the plurality of memory cells; a plurality of column lines electrically connected to the e-fuse devices through the switch devices of the plurality of memory cells; a row circuit configured to supply the high voltage to a program/read line corresponding to a selected row when a program operation is performed, supply a read voltage, which is lower than the high voltage, to a program/read line corresponding to a selected row when a read operation is performed, supply the ground voltage to a row line corresponding to a selected row when program and read operations are performed, and supply the negative voltage to program/read lines and row lines corresponding to unselected rows when program and read operations are performed; and a column circuit configured to supply the negative voltage to a column line corresponding to a selected column when program and read operations are performed.
7. The e-fuse array circuit of claim 6 , wherein the column circuit supplies the ground voltage to column lines corresponding to unselected columns when program and read operations are performed.
8. The e-fuse array circuit of claim 6 , wherein the column circuit comprises: a column decoder configured to select one or more of the plurality of columns in response to a column address; and a sense amplifier configured to supply the negative voltage to a column line selected by the column decoder when program and read operations are performed, check whether or not an electric current flows through the selected column line when a read operation is performed, and determine data of the selected column line based on a result of the check.
9. The e-fuse array circuit of claim 6 , wherein the read voltage is divided from the power source voltage.
10. The e-fuse array circuit of claim 6 , wherein the read voltage is the power source voltage.
11. The e-fuse array circuit of claim 6 , wherein the high voltage has a level of approximately 3.5 to 4.5V, the read voltage has a level of approximately 1.0 to 2.0V, and the negative voltage has a level of approximately −1.5 to −2.5V.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 8, 2012
November 4, 2014
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