A method of erasing a non-volatile memory (NVM) array includes determining a first number based on a temperature of the NVM array. Erase pulses of the first number are applied to the NVM array. A first verify of the NVM is performed for a first time after commencing the applying after the first number has been reached.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of erasing a non-volatile memory (NVM) array, comprising: determining a first number based on a temperature of the NVM array; applying erase pulses of the first number to the NVM array; and performing a first verify of the NVM for a first time after commencing the applying after the first number has been reached.
2. The method of claim 1 further comprising: if the performing the first verify determines erase was not successful, applying an additional erase pulse to the NVM array followed by a verification.
3. The method of claim 1 , further comprising: determining if the first number should be updated based on a number of erase pulses required to successfully erase the NVM array.
4. The method of claim 1 , further comprising: if the performing the first verify determines erase was not successful, alternately applying erase pulses and performing verifies until one of a group consisting of a determination that the erase has been successful or a failure to erase has occurred after a maximum number of erase pulses have been applied.
5. The method of claim 4 , wherein the determining is further characterized by the first number being further based on a number of erase cycles already performed.
6. The method of claim 1 , wherein the determining is further characterized by the first number being further based on a number of erase cycles already performed.
7. The method of claim 1 , wherein the determining is further characterized by the first number being selected from a plurality of numbers, wherein the plurality of numbers correspond to temperature ranges.
8. The method of claim 7 , wherein the determining is further characterized by each of the plurality of numbers is affected by changes in the number of pulses required to achieve an erase at the temperature range to which it corresponds.
9. The method of claim 8 , wherein the determining is further characterized by each of the plurality of numbers being a percentage of the number of pulses required to achieve an erase at the temperature range to which it corresponds.
10. The method of claim 1 , wherein: if the performing the first verify determines erase was not successful, alternately applying erase pulses and performing verifies until one of a group consisting of a determination that the erase has been successful or a failure to erase has occurred after a maximum number of erase pulses have been applied; if the erase has been successful, performing a compaction verify on the NVM array; and if compaction verify did not pass, performing compaction on the NVM array.
11. A non-volatile memory (NVM), comprising: an NVM array; charge pumps that provide a power supply for use in generating erase pulses; a temperature sensor that provides a signal indicative of a temperature of the NVM array; a controller, coupled to the NVM array, the temperature sensor, and the charge pumps that: determines a first number based on a temperature of the NVM array; applies erase pulses of the first number to the NVM array; and performs, for a first time after the first number of erase pulses has been reached, a first verify of the NVM.
12. The NVM of claim 11 , wherein if the controller determines erase was not successful, the controller alternately applies erase pulses and performs verifies until one of a group consisting of a determination that the erase has been successful or a maximum number of erase pulses has occurred.
13. The NVM of claim 12 , wherein the first number is further based on a number of erase cycles already performed.
14. The NVM of claim 13 , wherein the first number is selected from a plurality of numbers, wherein the plurality of numbers correspond to temperature ranges.
15. The method of claim 14 , wherein each of the plurality of numbers is affected by changes in the number of pulses required to achieve an erase at the temperature range to which it corresponds.
16. The method of claim 15 , wherein each of the plurality of numbers is a percentage of the number of pulses required to achieve an erase at the temperature range to which it corresponds.
17. A method of erasing a non-volatile memory (NVM) array, comprising; determining a first number of erase pulses to be applied to the NVM array based on a temperature of the NVM; applying the first number of erase pulses to the NVM array; determining if the first number of erase pulses has been applied to the NVM array; in response to determining that the first number of erase pulses has been applied to the NVM array, verifying if NVM array has been successfully erased.
18. The method of claim 17 , further comprising, if the NVM has not been successfully erased: applying a first additional erase pulse to the NVM array; and verifying if the NVM array has been successfully erased after the first additional erase pulse has been applied.
19. The method of claim 18 , further comprising, if the NVM array has not been successfully erased after the first additional erase pulse has been applied: applying further additional erase pulses to the NVM array until the NVM has been successfully erased or a maximum erase pulse count has been reached, wherein each further additional erase pulse is followed by verifying if the NVM array has been successfully erased.
20. The method of claim 17 , wherein the determining is further characterized by basing the first number on a number of erase pulses previously required to successfully erase the NVM array.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 30, 2013
November 4, 2014
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