A memory interleaving device includes a slave interface, a master interface, and a crossbar switch. The slave interface is connected with a master intellectual property through an on-chip network. The master interface is connected with a slave intellectual property. The crossbar switch connects the slave interface with the master interface. The memory interleaving device transmits requests from the master intellectual property to the slave intellectual property, receives data or responses respectively corresponding to the requests from the slave intellectual property, and transmits the data or responses to the master intellectual property in an order in which the requests are received.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory interleaving device comprising: a slave interface connected with a master intellectual property through an on-chip network; a master interface connected with a slave intellectual property; and a crossbar switch configured to connect the slave interface with the master interface, wherein the memory interleaving device transmits requests from the master intellectual property to the slave intellectual property, receives data or responses respectively corresponding to the requests from the slave intellectual property, reorders the received data or responses to an order in which the corresponding requests were received, and transmits the reordered data or responses to the master intellectual property.
2. The memory interleaving device of claim 1 , wherein the slave interface comprises: an R channel block comprising a reorder buffer configured to store read data received from the slave intellectual property in response to a read memory request of the master intellectual property, a first selector configured to output the read data in order, and a first storage unit configured to store an ID and a direction of the read memory request; and an AR channel block comprising an address decoder configured to decode an address of the read memory request and a second selector configured to transmit a decoded address to the slave intellectual property, and wherein the master interface comprises: an AR channel block comprising a third selector configured to transmit the decoded address of the read memory request from the crossbar switch to the slave intellectual property; and an R channel block comprising a fourth selector configured to transmit the read data from the slave intellectual property to the slave interface.
3. The memory interleaving device of claim 1 , wherein the slave interface comprises: an AW channel block comprising an address decoder configured to decode an address of a write memory request of the master intellectual property and a first selector configured to transmit a decoded address to the slave intellectual property; a W channel block comprising a first Wdata-pathQ configured to receive direction information extracted by the address decoder and control information extracted from write data and a second selector configured to receive the write data and output the write data to the slave intellectual property in response to a control signal output from the first Wdata-pathQ; and a B channel block comprising a reorder buffer configured to store a write response received from the slave intellectual property in response to the write memory request, a second storage unit configured to store an ID and a direction of the write memory request, and a third selector configured to output outputs of the reorder buffer in order, and wherein the master interface comprises: an AW channel block comprising a fourth selector configured to transmit the decoded address of the write memory request from the crossbar switch to the slave intellectual property; a W channel block comprising a fifth selector configured to transmit the write data from the crossbar switch to the slave intellectual property in response to a control signal and a second Wdata-pathQ configured to remember an order in which the write memory request has been received and output the control signal based on the order; and a B channel block comprising a sixth selector configured to transmit the write response from the slave intellectual property to the slave interface.
4. The memory interleaving device of claim 2 , wherein the reorder buffer comprises as many slots as a read acceptance capability of an input channel.
5. The memory interleaving device of claim 3 , wherein the reorder buffer comprises as many slots as a write acceptance capability of an input channel.
6. The memory interleaving device of claim 4 , wherein each of the slots comprises a data buffer sized as a multiple of a predetermined maximum burst length.
7. The memory interleaving device of claim 5 , wherein each of the slots comprises a buffer sized to store a BVALID field and a BRESP field.
8. The memory interleaving device of claim 4 , wherein when the AR channel block of the slave interface receives the ID and the direction of the read memory request in the first storage unit, the reorder buffer allocates one slot among the slots and stores the ID and the direction and the read data transmitted from the R channel block of the master interface in the slot.
9. The memory interleaving device of claim 7 , wherein when the AW channel block of the slave interface receives the ID and the direction of the write memory request in the second storage unit, the reorder buffer allocates one slot among the slots and stores the ID and the direction and the write response transmitted from the B channel block of the master interface in the slot.
10. The memory interleaving device of claim 8 , wherein the allocated slot is linked to other slots having the same ID as the slot in a linked list in the order in which the read memory request is received.
11. The memory interleaving device of claim 9 , wherein the allocated slot is linked to other slots having the same ID as the slot in a linked list in order in which the write memory request is received.
12. The memory interleaving device of claim 10 , wherein the reorder buffer detects slots having the same ID and direction as the read memory request, stores read data in a data buffer of a slot that has an oldest read memory request among the detected slots, and detects a subsequent slot according to the linked list after the read data is completely stored in the data buffer.
13. The memory interleaving device of claim 11 , wherein the reorder buffer detects slots having the same ID and direction as the write memory request, stores the write response in the BRESP field of a slot that has an oldest write memory request among the detected slots, and detects a subsequent slot according to the linked list after the write response is completely stored in the BRESP field.
14. The memory interleaving device of claim 12 , wherein the reorder buffer subjects the slot having the oldest read memory request among slots, which have the same ID and read data, to arbitration to transmit the read data to the on-chip network.
15. A memory interleaving method comprising: a master intellectual property transmitting a read memory request to a slave interface of a memory interleaving device through an on-chip network; the slave interface decoding an address of the read memory request, outputting the decoded address to a master interface of the memory interleaving device that is connected with a slave intellectual property corresponding to the read memory request, and storing ID and direction information of the read memory request into a reorder buffer; the reorder buffer allocating a slot for the ID and the direction information; the master interface transmitting the decoded address to the slave intellectual property corresponding to the read memory request; the slave intellectual property reading data corresponding to the read memory request and transmitting the data to the master interface; the master interface transmitting the data to the slave interface that has transmitted the read memory request; the reorder buffer storing the data received from the slave interface into the slot allocated for the ID and the direction information; subjecting an oldest slot among slots of the reorder buffer having the same ID and direction information as the read memory request to arbitration after a data transaction is completed; and the slave interface transmitting in order data subjected to the arbitration to the master intellectual property, which has transmitted the read memory request, through the on-chip network.
16. A memory interleaving device comprising: a slave interface connected with a plurality of master intellectual properties IPs; a master interface connected with a plurality of slave IPs; and a crossbar switch configured to exchange data between the master IPs and the slave IPs, wherein the memory interleaving device is configured to determine an order in which requests are received from the master IPs for slave IPs, transmit the requests to the corresponding slave IPs, receive corresponding messages from the slave IPs for each request in response to the transmitted requests, re-order the messages to correspond with the determined order, and output the re-ordered messages to the corresponding master IPs.
17. The memory interleaving device of claim 16 , wherein the slave interface comprises: a reorder buffer configured to store the re-ordered messages; a first selector configured to sequentially output the re-ordered messages; an address decoder configured to decode addresses of the requests; and a second selector configured to transmit the decoded addresses to the slave IPs.
18. The memory interleaving device of claim 17 , wherein the master interface comprises: a third selector configured to transmit the decoded addresses from the crossbar switch to the slave IPs; and a fourth selector configured to transmit the messages to the slave interface.
19. The memory interleaving device of claim 16 , wherein the slave interfaces comprises: an address decoder configured to decode an address of a write memory request of the master intellectual property; a first selector configured to transmit a decoded address to the slave intellectual property; a first Wdata-pathQ configured to receive direction information extracted by the address decoder and control information extracted from write data; a second selector configured to receive the write data and output the write data to the slave intellectual property in response to a control signal output from the first Wdata-pathQ; a reorder buffer configured to store a write response received from the slave intellectual property in response to the write memory request; a second storage unit configured to store an ID and a direction of the write memory request; and a third selector configured to output outputs of the reorder buffer in order.
20. The memory interleaving device of claim 19 , wherein the master interfaces comprises: a fourth selector configured to transmit the decoded address of the write memory request from the crossbar switch to the slave intellectual property; a fifth selector configured to transmit the write data from the crossbar switch to the slave intellectual property in response to a control signal; a second Wdata-pathQ configured to remember an order in which the write memory request has been received and output the control signal based on the order; and a sixth selector configured to transmit the write response from the slave intellectual property to the slave interface.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 12, 2011
November 11, 2014
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.