Methods for generating code for an architecture encoding an extended register specification

1. A method for generating code for a fixed-width instruction set, comprising: identifying a non-contiguous register specifier that includes at least two sets of contiguous bits separated by at least one bit not part of the register specifier; encoding a single logical register specifier into at least two non-contiguous fields of the non-contiguous register specifier, wherein the single logical register specifier is represented using a generic intrinsic that provides no indication of a partitioning of an operand specification into the non-contiguous register specifier; and generating a fixed-width instruction word that includes the non-contiguous register specifier.

2. The method of claim 1 , wherein a first set of bits in the non-contiguous register specifier is specified directly by an instruction field in the fixed-width instruction, and a second set of bits in the non-contiguous register specifier is specified directly by another instruction field in the fixed-width instruction.

3. The method of claim 1 , wherein a first set of bits in the non-contiguous register specifier is specified directly by an instruction field in the fixed-width instruction, a second set of bits in the non-contiguous register specifier is specified using a deep encoding, and the method further comprises generating a set of n bits for inclusion as part of the non-contiguous register specifier from a set of m bits encoded in the fixed-width instruction, wherein n is less than in, and the deep encoding involves allocating multiple opcode points or extended opcode points to indicate the fixed-width instruction, wherein each of the opcode points or the extended opcode points further indicates the use of a specific bit string as an extended register specifier.

4. The method of claim 1 , further comprising: generating a first set of fixed-width instructions that allow referencing of a first set of registers with a contiguous register specifier; and generating a second set of fixed-width instructions that allow referencing of a second set of registers using the non-contiguous register specifier, the second set of registers being larger than the first set of registers.

5. The method of claim 4 , wherein the second set of registers includes at least a subset of the first set of registers, the at least subset of the first set of registers being encoded by the second set of fixed-width instructions.

6. The method of claim 5 , further comprising generating the second set of fixed-width instructions using a compiling method for an extended register specification, the compiling method comprising allocating a first set of operands to the first set of registers, and allocating a second set of operands to the second set of registers, said allocating steps performed in accordance with an instruction set specification corresponding to the fixed-width instruction set.

7. A computer program product comprising a non-transitory computer usable medium having computer usable program code for generating code for a fixed-width instruction set, said computer program product comprising: computer usable program code for identifying a non-contiguous register specifier that includes at least two sets of contiguous bits separated by at least one bit not part of the register specifier; computer usable program code for encoding a single logical register specifier into at least two non-contiguous fields of the non-contiguous register specifier, wherein the single logical register specifier is represented using a generic intrinsic that provides no indication of a partitioning of an operand specification into the non-contiguous register specifier; and computer usable program code for generating a fixed-width instruction word that includes the non-contiguous register specifier.

8. The computer program product of claim of claim 7 , wherein a first set of bits in the non-contiguous register specifier is specified directly by an instruction field in the fixed-width instruction, and a second set of bits in the non-contiguous register specifier is specified directly by another instruction field in the fixed-width instruction.

9. The computer program product of claim of claim 7 , wherein a first set of bits in the non-contiguous register specifier is specified directly by an instruction field in the fixed-width instruction, a second set of bits in the non-contiguous register specifier is specified using a deep encoding, and the computer program product further comprises computer usable program code for generating a set of n bits for inclusion as part of the non-contiguous register specifier from a set of m bits encoded in the fixed-width instruction, wherein n is less than m, and the deep encoding involves allocating multiple opcode points or extended opcode points to indicate the fixed-width instruction, wherein each of the opcode points or the extended opcode points further indicates the use of a specific bit string as an extended register specifier.