Adjustable voltage regulator calibration circuit

1. An integrated circuit comprising: a plurality of adjustable voltage regulators; a selection circuit operable to select one of a reference voltage or a voltage of a voltage regulator from the plurality of adjustable voltage regulators to form a selected output voltage, the reference voltage is a power supply voltage of a data path, the voltage regulator is a power supply of a clock path; an analog to digital converter operable to convert the selected output voltage to form a digital selected output voltage, wherein said analog to digital converter is further operable to convert the reference voltage to form a digital reference voltage; and a state machine operable to receive the digital selected output voltage and the digital reference voltage from the analog to digital converter, wherein the state machine is further operable to determine whether the digital selected output voltage, formed with the selection circuit selecting the voltage of the voltage regulator, matches the digital reference voltage and to adjust the voltage regulator that is the power supply of the clock path until a power supply voltage of the clock path is within a predefined range of the power supply voltage of the data path wherein the predefined range is determined by a number of control bits.

2. The integrated circuit of claim 1 , wherein the state machine further comprises: a comparator operable to compare the digital reference voltage and the digital selected output voltage, and wherein the state machine is operable to recursively adjust the selected output voltage based on an output of the comparator.

3. The integrated circuit of claim 1 , wherein the state machine further comprises: a lookup table operable to store the digital reference voltage.

4. The integrated circuit of claim 3 further comprising: a core logic of a programmable logic device coupled to an output of the analog to digital converter, wherein the state machine and the lookup table are implemented in the core logic of the programmable logic device.

5. The integrated circuit of claim 1 , wherein the state machine is operable to provide a selection signal to the selection circuit for selecting one of the reference voltage or a new voltage of a voltage regulator from the plurality of adjustable voltage regulators to form an updated selected output voltage.

6. The integrated circuit of claim 1 , wherein each of the adjustable voltage regulators further comprises: a control bus having a width greater than one bit, the control bus coupled to the analog state machine.

7. The integrated circuit of claim 1 , wherein the state machine is operable to successively select each of the plurality of output voltages associated with the plurality of adjustable voltage regulators and the reference voltage through the selection circuit.

8. The integrated circuit of claim 1 , wherein: the integrated circuit is implemented in a programmable logic device; a clock of the clock path is operable to clock a portion of the data path; and the state machine is further operable to match the voltage of the voltage regulator to the reference voltage, which matches the power supply of the clock path to the power supply of the data path.

9. A calibration circuit comprising: an analog multiplexer having a plurality of input terminals, the plurality of input terminals coupled to a reference voltage and an output voltage associated with an adjustable voltage regulator, the reference voltage is a supply voltage of a data path, the output voltage is a supply voltage of a clock path; and a state machine having a lookup table for storing a digital value of the reference voltage, wherein the state machine is operable to compare the output voltage to the stored digital reference voltage, and wherein the state machine is operable to adjust the output voltage until the supply voltage of the clock path is within a predefined range of the supply voltage of the data path, based on the comparison by transmitting a control signal to the adjustable voltage regulator, wherein the predefined range is determined by a number of control bits.

10. The calibration circuit of claim 9 , wherein the adjustable voltage regulator further comprises: a control input operable to receive the control signal from the state machine for adjusting the output voltage of the adjustable voltage regulator, wherein a voltage step of the adjustable voltage regulator is determined by a number of bits associated with the control signal.

11. The calibration circuit of claim 10 , wherein the state machine is operable to terminate adjusting the output voltage when the output voltage is within a range of the reference voltage, wherein the range is defined by the voltage step.

12. The calibration circuit of claim 10 , wherein the analog multiplexer is coupled to an analog test bus, wherein the analog test bus is operable to provide selective access to the output voltage through a bondpad.

13. The calibration circuit of claim 9 , wherein the analog multiplexer further comprises: a plurality of address inputs operable to receive a plurality of selection bits from the state machine, wherein the plurality of selection bits is used to select one of the output voltage or the reference voltage.

14. The calibration circuit of claim 9 , wherein: the reference voltage is a power supply for a data path; the adjustable voltage regulator is one of a plurality of adjustable voltage regulators coupled to the analog multiplexer; a portion of the data path is clocked by a clock from the clock path; and the output voltage is recursively adjusted until the supply voltage of the data path matches the supply voltage of the clock path to within a predetermined range.

15. The calibration circuit of claim 9 , wherein the state machine further comprises: a comparator operable to compare the stored reference voltage and the output voltage.

16. A method of dynamically calibrating an output voltage of an adjustable voltage regulator to a reference voltage, the method comprising: selecting one of a plurality of analog voltages to form a selected output voltage, wherein each analog voltage of the plurality of analog voltages corresponds to an output voltage of an adjustable voltage regulator, wherein one analog voltage of the plurality of analog voltages is a power supply voltage of a clock path, wherein the selecting is based on a plurality of selection bits; comparing a reference voltage with the selected output voltage, the reference voltage is a power supply voltage of a data path; and adjusting the adjustable voltage regulator corresponding to the analog voltage that is the power supply voltage of the clock path, until the power supply voltage of the clock path is within a predefined range of the power supply voltage of the data path wherein the predefined range is determined by a number of control bits.

17. The method of claim 16 further compromising: cycling through a default sequence of the plurality of selection bits to select each of the plurality of analog voltages to compare with the reference voltage, the cycling including selecting the analog voltage provided by the power supply of the clock path, wherein an adjustable voltage regulator of the power supply of the clock path is recursively adjusted until the analog voltage provided by the power supply of the clock path is within the predefined range of the reference voltage.

18. The method of claim 16 further comprising: receiving the plurality of selection bits from an analog monitor state machine, and wherein the selecting is performed in a successive manner.

19. The method of claim 16 further comprising: converting the selected output voltage into a digital value; and transmitting the digital value of the selected output voltage to an analog monitor state machine.

20. The method of claim 19 further comprising: storing a digital value of the reference voltage in a lookup table, wherein the comparing utilizes the stored digital value of the reference voltage and a digital value associated with the selected output voltage.