Semiconductor device and image processing method

1. A semiconductor device comprising: an image processing unit that includes at least two output terminals; a data combination unit that combines data from the at least two output terminals of the image processing unit and outputs the combined data to a terminal, a number of the terminal being smaller than a number of the output terminals of the image processing unit; an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus; and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

2. A semiconductor device comprising: an image processing unit that includes at least two output terminals; a data combination unit that outputs combined data obtained by combining data from the at least two output terminals of the image processing unit; an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, a number of the output buffer being smaller than a number of the output terminals of the image processing unit; and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.

3. The semiconductor device according to claim 1 , wherein the output buffer is provided for each output terminal of the data combination unit.

4. The semiconductor device according to claim 1 , wherein the data distribution unit includes: a data division unit that divides the combined data supplied from the output buffer; and a selector that selects and outputs either the combined data or divided data divided by the data division unit based on the combination distribution instruction.

5. The semiconductor device according to claim 4 , wherein the data distribution unit further includes an address generation unit that generates an address of the combined data or the divided data based on the combination distribution instruction.

6. The semiconductor device according to claim 4 , wherein the data distribution unit further includes a data distribution adjustment unit that adjusts data divided by the data division unit into a predetermined size.

7. The semiconductor device according to claim 5 , wherein the address generation unit includes: a base address generation unit that generates a base address; an offset giving unit that gives an offset to the base address; and a first selector that selects and outputs one of the base address generated by the base address generation unit and an offset address obtained by giving the offset to the base address in the offset giving unit.

8. The semiconductor device according to claim 7 , wherein the image processing unit produces at least two calculation results for one pixel, and the address generation unit further includes a plurality of types of offset giving units that give different offset values, and a second selector that selects whether the base address and a plurality of offset addresses generated by the plurality of offset giving units are output as division addresses of the divided data or the base address is output as a combination address of the combined data.

9. A method of processing an image, the method comprising: an image data calculation step for calculating at least two types of image data by using an image processing unit; a combination step for combining the at least two types of image data calculated in the image data calculation step; a buffering step for supplying combined data combined in the combination step to one output buffer, and buffering the combined data until an output permission is issued from bus arbitration means; and a data distribution step for outputting the combined data, which is permitted to be output from the output buffer, to a bus in a form of the combined data, or distributing the combined data and outputting the distributed data to the bus based on a combination distribution instruction.

10. The method according to claim 9 , wherein the data distribution step includes: a data division step for dividing the combined data supplied from the output buffer; and an output step for selecting and outputting either the combined data or divided data divided in the data division step based on the combination distribution instruction.

11. The method according to claim 10 , wherein the data distribution step includes an address generation step for generating an address of the combined data or the divided data based on the combination distribution instruction.

12. The method according to claim 11 , wherein in the address generation step, addresses of the combined data and the divided data are generated by generating a base address, generating an offset address by giving an offset to the base address, and selecting and outputting one of the base address and the offset address.

13. The method according to claim 12 , wherein in the address generation step, a plurality of types of offset addresses are generated by giving offsets having different values to the base address, and the base address and the plurality of offset addresses are successively output as division addresses of the divided data, or the base address is output as a combination address of the combined data according to the combination distribution instruction.

14. An information processing apparatus comprising: a memory interface that connects to an external memory; a semiconductor device that connects to the memory interface through a bus; a bus arbitration unit that arbitrates the bus; and a general-purpose arithmetic unit that controls the semiconductor device, wherein the semiconductor device includes: an image processing unit including at least two output terminals; a data combination unit that combines data from the at least two output terminals of the image processing unit and outputs the combined data to a terminal, a number of the terminal being smaller than a number of the output terminals of the image processing unit; an output buffer that adjusts an output timing of the combined data according to an instruction supplied from the bus arbitration unit that arbitrates the bus; and a data distribution unit that outputs the combined data supplied from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to a combination distribution instruction supplied from the general-purpose arithmetic unit.

15. The information processing apparatus according to claim 14 , further comprising a camera interface that is connected to an external image-pickup device.