Non-volatile memory (NVM) systems and related methods adjust program/erase bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store performance degradation information and program/erase bias condition information within storage circuitry. The disclosed embodiments adjust program/erase bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations and interim verify based performance degradation determinations.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated non-volatile memory (NVM) system, comprising: an array of non-volatile memory (NVM) cells; bias voltage generator circuitry configured to generate bias voltages for the NVM cells; controller circuitry configured to determine performance degradation for the NVM system based upon an interim verify operation relating to at least one of a program operation or an erase operation conducted after a predetermined number of program or erase pulses and before a maximum number of program or erase pulses is reached and to adjust at least one voltage level for the bias voltages generated by the bias voltage generator circuitry based upon results of the interim verify operation, the interim verify level for the interim verify operation being a voltage level between a default erase verify voltage level and a default program verify voltage level; wherein the controller circuitry is further configured to continue the at least one of a program operation or an erase operation for the NVM system using the at least one adjusted voltage level after the interim verify operation.
2. The integrated NVM system of claim 1 , wherein the controller circuitry is further configured to obtain performance information for the NVM system, the performance information comprising at least one of cycle count, program pulse count, or erase pulse count.
3. The integrated NVM system of claim 1 , wherein the at least one adjusted voltage level is a voltage level for a gate bias voltage, a body bias voltage, or a drain bias voltage, or a combination of these bias voltages.
4. The integrated NVM system of claim 1 , wherein the at least one voltage level comprises a voltage level for a gate bias voltage for a program operation.
5. The integrated NVM system of claim 4 , wherein the program operation comprises a soft-program operation.
6. The integrated NVM system of claim 4 , wherein the gate bias voltage level is increased by an amount less than or equal to 500 milli-volts.
7. The integrated NVM system of claim 1 , wherein the at least one voltage level comprises a voltage level for a body bias voltage for an erase operation.
8. The integrated NVM system of claim 7 , wherein the erase bias voltage level is increased by an amount less than or equal to 500 milli-volts.
9. The integrated NVM system of claim 1 , wherein the bias voltage generator circuitry comprises at least two circuit blocks positioned in different locations on the integrated NVM system.
10. The integrated NVM system of claim 1 , further comprising storage circuitry configured to store sets of bias condition parameters, and wherein the controller circuitry is configured to use at least one set of stored bias condition parameters to adjust the at least one voltage level.
11. The integrated NVM system of claim 2 , further comprising storage circuitry configured to store performance degradation information, and wherein the controller circuitry is configured to compare the performance information to stored performance degradation information to make a performance degradation determination.
12. The integrated NVM system of claim 11 , wherein the stored performance degradation information is temperature-based performance degradation information, wherein the controller circuitry is further configured to obtain operating temperature information for the NVM system, and wherein the controller circuitry is further configured to determine performance degradation by comparing the performance information to the temperature-based performance degradation information.
13. The integrated NVM system of claim 1 , wherein the controller circuitry is further configured to set a flag if the interim verify operation is a failure to indicate that a performance degradation condition exists for the NVM system.
14. The integrated NVM system of claim 1 , wherein the performance information comprises results of a plurality of interim verify operations.
15. A method for operating an integrated non-volatile memory (NVM) system, comprising: performing an interim verify operation for an array of non-volatile memory (NVM) cells within an NVM system during a program or erase operation after a predetermined number of program or erase pulses and before a maximum number of program or erase pulses is reached, the interim verify level for the interim verify operation being a voltage level between a default erase verify voltage level and a default program verify voltage level, determining performance degradation based upon the interim verify operation; adjusting at least one bias voltage generated by a bias voltage generator for the NVM cells based upon the performance degradation determination; and performing at least one of a program operation or an erase operation for the NVM system using the adjusted at least one bias voltage.
16. The method of claim 15 , further comprising obtaining performance information for the NVM system, wherein the performance information comprises at least one of cycle count, program pulse count or erase pulse count.
17. The method of claim 16 , further comprising obtaining operating temperature information for the NVM system, and determining performance degradation for the NVM system using a comparison of the performance information with temperature-based performance degradation information associated with at least one of program pulse counts, erase pulse counts, or cycle counts.
18. The method of claim 15 , wherein the adjusting step comprises increasing a voltage level for a gate bias voltage, and wherein a program operation is performed using the increased gate bias voltage level.
19. The method of claim 15 , wherein the adjusting step comprises increasing a voltage level for a base bias voltage, and wherein an erase operation is performed using the increased body bias voltage level.
20. The method of claim 15 , further comprising performing a plurality of interim verify operations.
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July 25, 2012
December 2, 2014
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