A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method comprising: providing shallow trench isolation (STI) regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming carbon-doped silicon (Si:C) on the silicon wafer in the recess.
2. The method according to claim 1 , comprising forming the recess by reactive ion etching (RIE).
3. The method according to claim 1 , comprising forming the recess by an anisotropic wet etch.
4. The method according to claim 1 , comprising annealing the silicon wafer prior to forming the Si:C in the recess.
5. The method according to claim 1 , comprising forming the shallow well implantation at an energy of 5 kiloelectronvolts (keV) to 30 keV and at a dose of 2E13 to 1E14.
6. The method according to claim 1 , comprising forming the Si:C in the recess by epitaxially growing carbon-doped silicon (Si:C) to a thickness of 2 nanometers (nm) to 15 nm.
7. The method according to claim 6 , further comprising epitaxially growing silicon to a thickness of 2 nm to 15 nm on the Si:C.
8. The method according to claim 1 , comprising forming the Si:C in the recess by: epitaxially growing silicon to a thickness of 3 nm to 15 nm in the recess; amorphizing the epitaxially grown silicon; implanting carbon in the amorphized silicon; and thermally treating the implanted amorphized silicon.
9. The method according to claim 8 , comprising amorphizing the silicon by implanting germanium (Ge).
10. The method according to claim 8 , comprising thermally treating the implanted amorphized silicon by performing a spike rapid thermal anneal (RTA).
11. The method according to claim 8 , further comprising epitaxially growing undoped silicon to a thickness of 0 nm to 15 nm in the recess subsequent to thermally treating the implanted amorphized silicon.
12. A method comprising: providing shallow trench isolation (STI) regions in a silicon wafer; performing a deep well implantation of a p-type dopant into the silicon wafer between the STI regions; recessing the silicon wafer to a depth of 10 nanometers (nm) to 25 nm between the STI regions; implanting a p-type dopant into the silicon wafer between the STI regions at an energy of 5 kiloelectronvolts (keV) to 30 keV and at a dose of 2E13 to 1E14; forming carbon-doped silicon (Si:C) on the doped silicon between the STI regions by: epitaxially growing Si:C or epitaxially growing undoped silicon, implanting germanium (Ge) in the undoped silicon, implanting carbon in the Ge doped silicon, and performing a spike rapid thermal anneal (RTA); and epitaxially growing undoped silicon on the Si:C to a thickness of 0 nm to 15 nm.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 17, 2013
December 23, 2014
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