Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor device comprising: providing a semiconductor substrate with a first semiconductor fin and a second semiconductor fin, the first and second semiconductor fins extending, with respect to a top down view, in a first direction and extending along a same line and defining a first recess between facing ends of the first and second semiconductor fins; forming a first insulator pattern about sidewalls of the first and second semiconductor fins and in the first recess; forming a second insulator pattern on the first insulator pattern at a location above the first recess; etching the first insulator pattern and the second insulator pattern so that the top surfaces of the first and second fins extend above a top surface of the etched first insulator pattern and so that a top surface of remaining insulator in the first recess is above the top surface of the etched first insulator pattern; forming a first gate electrode to extend over the first semiconductor fin, a second gate electrode to extend over the second semiconductor fin, and a first dummy gate to extend over the remaining insulator in the first recess.
2. The method of claim 1 , wherein the forming a second insulator pattern on the first insulator pattern comprises: forming a hard mask layer over the first and second semiconductor fins and the first insulator pattern; forming an opening in the hard mask layer over the first recess, the opening being located over facing ends of the first and second semiconductor fins; depositing an insulator layer over the hard mask layer and in the opening in the hard mask layer; and removing the insulator layer over the hard mask layer to form the second insulator pattern.
3. The method of claim 2 , wherein the step of removing the insulator layer over the hard mask layer comprises a planarizing etching of the insulator layer to expose the hard mask layer.
4. The method of claim 2 , further comprising: etching portions of the first and second semiconductor fins exposed by the opening in the hard mask layer.
5. The method of claim 4 , wherein the opening in the hard mask layer exposes the facing ends of the first and second semiconductor fins.
6. The method of claim 2 , wherein the opening is linearly shaped and extends past plural pairs of neighboring parallel fins.
7. The method of claim 6 , further comprising: forming the second insulator pattern on the first insulator pattern in the linearly shaped opening; etching the first insulator pattern and the second insulator pattern so the remaining insulator extends along a length corresponding to the linearly shaped opening; and forming the dummy gate above the remaining insulator.
8. The method of claim 1 , wherein, with respect to a cross section of the remaining insulator taken along the first direction, the remaining insulator has a T-shape.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 5, 2014
December 23, 2014
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.