Inline fuses in programmable crossbar arrays

1. A programmable crossbar array with inline fuses comprising: a layer of row lines; a layer of column lines, the row lines crossing over the column lines to Form junctions; resistive memory elements sandwiched between row lines and column lines at the junctions; support circuitry; and inline fuses in either the row lines, column lines or both, the inline fuses interposed between the support circuitry and the resistive memory elements.

2. The array of claim 1 , in which inline fuses are connected inline with only one of: the row lines and the column lines.

3. The array of claim 1 , in which the inline fuses are connected inline in both the row lines and the column lines.

4. The array of claim 1 , further comprising a separate line connected to the row and column lines on an inner terminal of fuses in the row and column lines, such that when a resistive memory element shorts, a ground is connected to the inner terminal of the fuse via the separate line.

5. The array of claim 1 , in which an inline fuse connected to a line is caused to blow when a resistive memory element connected to the line shorts, in which the blown fuse serves as: a flag marking shorted resistive memory elements for error correction code to recover data stored in a shorted resistive memory element and in resistive memory elements in the same row and column as the shorted resistive memory element; and to prevent application of programming and reading voltages to the line connected to the shorted resistive memory element.

6. The array of claim 1 , in which the support circuitry comprises a voltage source, a current sensor, and a ground.

7. The array of claim 6 , further comprising a switch for switching row and column connections between different support circuitry components.

8. The array of claim 6 , further comprising an array read configuration in which the voltage source is applied to a selected row line with a remainder of the row lines connected to ground and the current sensors are connected to all of the column lines, in which a voltage applied to the selected row line creates currents passing through resistive devices connected to the row line, the currents passing down the column lines to be sensed by the current sensors.

9. The array of claim 6 , further comprising an array write configuration comprising a portion of a programming voltage applied to a selected row line and a portion of the programming voltage is applied to a selected column line, in which a complete programming voltage is applied across a target device interposed between the selected row line and selected column line.

10. A method comprising: detecting a shorted memristor in a crossbar array, in which the shorted Memristor is connected to a row line and column line; and blowing a fuse inline with one of the row line or the column line.

11. The method of claim 10 , further comprising recovering data stored in the shorted memristor by identifying the location of the shorted memristor using the blown fuse.

12. The method of claim 11 , in which recovering data stored in the shorted memristor comprises: using an error correction code to recover data stored in the shorted memristor and other memristors in the same row and column as the shorted memristor; and copying the recovered data to a non-defective memory location.

13. The method of claim 10 , further comprising writing the data to the crossbar array by skipping write operations on the row and column connected to the shorted memristor.

14. The method of claim 10 , in which detecting a shorted memristor comprises a current surge through the shorted memristor that passes down a line and blows the fuse.

15. The method of claim 10 , further comprising executing a read operation by applying a read voltage to the crossbar array and connecting current sensors to the crossbar array to detect current passing through memristors in the array; when no current is detected in a line during the read operation, marking data stored in memristors connected to the line as erased; and recovering the data using error correction code.

16. The method of claim 10 , in which a first fuse is inline with a first line connected to the shorted memristor and a second fuse is inline with a second line connected to the shorted memristor, the method further comprising: blowing the first fuse by passing a current passing through the shorted memristor; and blowing the second fuse by a current that does not pass through the shorted memristor.

17. The method of claim 16 , in which blowing the second fuse comprises: grounding one end of the fuse; and applying voltage to the opposite end of the fuse.

18. The method of claim 10 , in which detecting the shorted memristor comprises detecting an abnormally low resistance of the shorted memristor.

19. The method of claim 10 , in which detecting the shorted memristor comprises detecting an abnormally high current passing through the shorted memristor.

20. The method of claim 10 , in which detecting the shorted memristor comprises: applying a read voltage to the row line in the crossbar array; when current does not flow through a first column line crossing the row line, marking data stored in the first column line as erased; when current does not flow through any columns lines crossing the row line, marking the data stored in the row line as erased; and recovering the data using error correction code.