A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: an n-type drain layer; an n-type base layer provided on the n-type drain layer; a p-type base layer partially formed in a surface layer portion of the n-type base layer; an n-type source layer partially formed in a surface layer portion of the p-type base layer; a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer; a gate electrode formed on the gate insulation film to face, through the gate insulation film, the surface of the p-type base layer between the n-type source layer and the n-type base layer; a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer; a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer so as to be within the n-type base layer, the depletion layer alleviation region including first baryons converted to donors; a trap level region including second baryons for forming a trap level to be locally formed within the depletion layer alleviation region, the second baryons being heavier than the first baryons; a source electrode electrically connected to the n-type source layer; and a drain electrode electrically connected to the n-type drain layer.
2. The device of claim 1 , wherein the depletion layer alleviation region has a thickness greater than a thickness of the trap level region.
3. The device of claim 1 , wherein the second baryons comprise one member selected from the group consisting of protons, 3 He ++ and 4 He ++ .
4. The device of claim 1 , wherein the first baryons comprise one member selected from the group consisting of protons, 3 He ++ and 4 He ++ .
5. The device of claim 1 , wherein the first baryons comprise protons.
6. The device of claim 1 , wherein the depletion layer alleviation region includes an area overlapping with the p-type column layer.
7. The device of claim 1 , wherein the depletion layer alleviation region does not include an area overlapping with the p-type column layer.
8. The device of claim 1 , wherein the depletion layer alleviation region is adjacent to the p-type column layer.
9. The device of claim 1 , wherein the depletion layer alleviation region is separated from the p-type column layer.
10. A power module, comprising: a high-side switching element formed of the semiconductor device of claim 1 ; and a low-side switching element formed of the semiconductor device of claim 1 , the high-side switching element and the low-side switching element being serially connected to each other.
11. The power module of claim 10 , wherein the high-side switching element comprises high-side switching elements and the low-side switching element includes low-side switching elements, the power module further comprising: three serial circuits each including one of the high-side switching elements and one of the low-side switching elements that are serially connected to each other, the three serial circuits being parallel-connected to one another.
12. The power module of claim 10 , wherein the power module is used to supply a drive current to an alternating current electric motor.
13. The device of claim 1 , wherein a parasitic diode is formed by a p-n junction between the p-type base layer, the p-type column layer and the n-type base layer, and the depletion layer alleviation region restraining a depletion layer from expanding from the p-n junction when the parasitic diode is turned off.
14. A semiconductor device, comprising: an n-type drain layer; an n-type base layer disposed on the n-type drain layer; a p-type base layer disposed in the n-type base layer; an n-type source layer disposed in the p-type base layer; a gate insulation film disposed on a surface of the p-type base layer between the n-type source layer and the n-type base layer; a gate electrode disposed on the gate insulation film disposed, through the gate insulation film, upon the surface of the p-type base layer; a p-type column layer disposed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer; a depletion layer alleviation region disposed between the p-type column layer and the n-type drain layer so as to be within the n-type base layer, the depletion layer alleviation region including first baryons converted to donors; a trap level region including second baryons for forming a trap level, the trap level region being disposed within the depletion layer alleviation region, the second baryons being heavier than the first baryons; a source electrode electrically connected to the n-type source layer; and a drain electrode electrically connected to the n-type drain layer.
15. The device of claim 14 , wherein a parasitic diode is formed by a p-n junction between the p-type base layer, the p-type column layer and the n-type base layer, and the depletion layer alleviation region restraining a depletion layer from expanding from the p-n junction when the parasitic diode is turned off.
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December 28, 2011
December 30, 2014
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