A system includes a memory with columns and rows. A sampler samples a first portion of a signal during first periods to obtain sets of samples, respectively. The sets of samples include a first set having first samples and a second set having second samples. A first controller writes each set in the sets of samples in a respective one of the columns. The first controller writes: the first samples in a first column such that each of the first samples is stored in a respective one of the rows; the second samples in a second column such that each of the second samples is stored in a respective one of the rows; and the second samples in the second column subsequent to writing the first samples in the first column. A second controller reads third samples stored in a first row and fourth samples stored in a second row.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A system comprising: a first memory comprising a first plurality of columns and a first plurality of rows; a sampler configured to sample a first portion of a signal during a first plurality of periods to obtain first sets of samples, respectively, wherein the first sets of samples comprise (i) a first set having a first plurality of samples, and (ii) a second set having a second plurality of samples; a first controller configured to write each set in the first sets of samples in a respective one of the first plurality of columns, wherein the first controller is configured to write the first plurality of samples in a first column of the first memory such that each of the first plurality of samples is stored in a respective one of the first plurality of rows, write the second plurality of samples in a second column of the first memory such that each of the second plurality of samples is stored in a respective one of the first plurality of rows, and write the second plurality of samples in the second column of the first memory subsequent to the writing of the first plurality of samples in the first column of the first memory; and a second controller configured to, subsequent to the first controller writing the first plurality of samples and the second plurality of samples in the first memory, read (i) a third plurality of samples stored in a first row of the first memory, and (ii) a fourth plurality of samples stored in a second row of the first memory.
2. The system of claim 1 , wherein: the second controller is configured to read the second row of the first memory subsequent to reading the first row of the first memory, the third plurality of samples comprises some of the first plurality of samples and some of the second plurality of samples, and the fourth plurality of samples comprises some of the first plurality of samples and some of the second plurality of samples.
3. The system of claim 1 , wherein: each sample in the first sets of samples includes a plurality of bits; and each entry in the plurality of columns stores the plurality of bits for a respective sample in the first sets of samples.
4. The system of claim 1 , wherein the first controller is configured to write the first sets of samples in the first plurality of rows of the first memory according to phase such that (i) each row has a respective phase of samples, (ii) samples in each of the plurality of rows of the first memory have a same phase, and (iii) samples in different rows of the first memory have different phases.
5. The system of claim 1 , further comprising an integrator configured to integrate the first sets of samples of the signal read from the first memory on a row-by-row basis to provide an integration result for each row of the first memory, wherein each of the integration results is a result of integrating samples read from entries in (i) the first plurality of columns, and (ii) a respective one of the first plurality of rows of the first memory.
6. The system of claim 5 , further comprising: a receiver configured to receive the signal from a transmitter, wherein the signal is modulated with a first waveform, and wherein the first sets of samples are of the first waveform; a correlator configured to correlate the integration results with a second waveform, wherein the second waveform is indicative of a pseudorandom number; an identification module configured to, based on an output of the correlator, identify the transmitter; and a location module configured to, based on the identity of the transmitter, determine a location of the system.
7. The system of claim 1 , further comprising a second memory having a second plurality of columns and a second plurality of rows, wherein: the sampler is configured to sample a second portion of the signal during a second plurality of periods to obtain second sets of samples, respectively, wherein the second sets of samples comprise (i) a third set having a fifth plurality of samples, and (ii) a fourth set having a sixth plurality of samples; the second controller is configured to write each set in the second sets of samples in a respective one of the second plurality of columns, wherein the second controller writes the fifth plurality of samples in a first column of the second memory such that each of the fifth plurality of samples is stored in a respective one of the second plurality of rows, writes the sixth plurality of samples in a second column of the second memory such that each of the sixth plurality of samples is stored in a respective one of the second plurality of rows, and writes the sixth plurality of samples in the second column of the second memory subsequent to writing the fifth plurality of samples in the first column of the second memory; and the second controller is configured to, subsequent to the second controller writing the fifth plurality of samples and the sixth plurality of samples in the second memory, read (i) a seventh plurality of samples stored in a first row of the second memory, and (ii) an eighth plurality of samples stored in a second row of the second memory.
8. The system of claim 7 , wherein: the second controller is configured to read the second row of the second memory subsequent to reading the first row of the second memory; the seventh plurality of samples comprises some of the fifth plurality of samples and some of the sixth plurality of samples; and the eighth plurality of samples comprises some of the fifth plurality of samples and some of the sixth plurality of samples.
9. The system of claim 8 , wherein the first controller is configured to write: the second sets of samples of the signal to the second memory subsequent to completing writing of the first sets of samples of the signal to the first memory; and subsequent to the second controller completing writing of the second portion of the signal to the second memory, third sets of samples for a third portion of the signal respectively in the first column of the first memory and the second column of the first memory.
10. The system of claim 8 , wherein the second controller is configured to: iteratively transition between (i) reading a row of the first memory and (ii) reading a row of the second memory; during a first iteration, read a first row of the first memory followed by reading a first row of the second memory; and during a second iteration, (i) read a second row of the first memory subsequent to reading the first row of the second memory, and (ii) read the second row of the second memory subsequent to reading the second row of the first memory.
11. A method comprising: sampling a first portion of a signal during a first plurality of periods to obtain first sets of samples, respectively, wherein the first sets of samples comprise (i) a first set having a first plurality of samples, and (ii) a second set having a second plurality of samples; writing each set in the first sets of samples in a respective one of a first plurality of columns of a first memory, wherein the first plurality of samples are written in a first column of the first memory such that each of the first plurality of samples is stored in a respective one of a first plurality of rows of the first memory, the second plurality of samples are written in a second column of the first memory such that each of the second plurality of samples is stored in a respective one of the first plurality of rows, and the second plurality of samples are written in the second column of the first memory subsequent to the writing of the first plurality of samples in the first column of the first memory; and subsequent to writing the first plurality of samples and the second plurality of samples in the first memory, reading (i) a third plurality of samples stored in a first row of the first memory, and (ii) a fourth plurality of samples stored in a second row of the first memory.
12. The method of claim 11 , wherein: the second row of the first memory is read subsequent to reading the first row of the first memory; the third plurality of samples comprises some of the first plurality of samples and some of the second plurality of samples; and the fourth plurality of samples comprises some of the first plurality of samples and some of the second plurality of samples.
13. The method of claim 11 , wherein: each sample in the first sets of samples includes a plurality of bits; and each entry in the plurality of columns stores the plurality of bits for a respective sample in the first sets of samples.
14. The method of claim 11 , wherein the first sets of samples of the signal are written to the first plurality of rows of the first memory according to phase such that (i) each row has a respective phase of samples, (ii) samples in each of the plurality of rows of the first memory have a same phase, and (iii) samples in different rows of the first memory have different phases.
15. The method of claim 11 , further comprising integrating the first sets of samples of the signal read from the first memory on a row-by-row basis to provide an integration result for each row of the first memory, wherein each of the integration results is a result of integrating samples read from entries in (i) the first plurality of columns, and (ii) a respective one of the first plurality of rows of the first memory.
16. The method of claim 15 , further comprising: receiving the signal from a transmitter, wherein the signal is modulated with a first waveform, and wherein the first sets of samples are of the first waveform; correlating the integration results with a second waveform, wherein the second waveform is indicative of a pseudorandom number; based on an output of the correlator, identifying the transmitter; and based on the identity of the transmitter, determining a location of the transmitter.
17. The method of claim 11 , further comprising: sampling a second portion of the signal during a second plurality of periods to obtain second sets of samples, respectively, wherein the second sets of samples comprise (i) a third set having a fifth plurality of samples, and (ii) a fourth set having a sixth plurality of samples; writing each set in the second sets of samples in a respective one of a second plurality of columns of a second memory, wherein the fifth plurality of samples are written in a first column of the second memory such that each of the fifth plurality of samples is stored in a respective one of a second plurality of rows of the second memory, the sixth plurality of samples are written in a second column of the second memory such that each of the sixth plurality of samples is stored in a respective one of the second plurality of rows, and the sixth plurality of samples are written in the second column of the second memory subsequent to writing the fifth plurality of samples in the first column of the second memory; and subsequent to writing the fifth plurality of samples and the sixth plurality of samples in the second memory, reading (i) a seventh plurality of samples stored in a first row of the second memory, and (ii) an eighth plurality of samples stored in a second row of the second memory.
18. The method of claim 17 , wherein: the second row of the second memory is read subsequent to reading the first row of the second memory; the seventh plurality of samples comprises some of the fifth plurality of samples and some of the sixth plurality of samples; and the eighth plurality of samples comprises some of the fifth plurality of samples and some of the sixth plurality of samples.
19. The method of claim 18 , wherein: the second sets of samples of the signal are written to the second memory subsequent to completing writing of the first sets of samples of the signal to the first memory; and subsequent to completing writing of the second portion of the signal to the second memory, third sets of samples for a third portion of the signal are written respectively in the first column of the first memory and the second column of the first memory.
20. The method of claim 18 , further comprising: iteratively transitioning between (i) reading a row of the first memory and (ii) reading a row of the second memory; during a first iteration, reading a first row of the first memory followed by reading a first row of the second memory; and during a second iteration, (i) reading a second row of the first memory subsequent to reading the first row of the second memory, and (ii) read the second row of the second memory subsequent to reading the second row of the first memory.
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August 16, 2013
December 30, 2014
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