One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a transistor, comprising: forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers; removing a portion of said sidewall spacers to define recessed sidewall spacers; removing a portion of said final gate structure to define a recessed final gate structure; performing a conformal deposition process to form a conformal etch stop layer on at least said recessed sidewall spacers and said recessed final gate structure, wherein said conformal etch shop layer defines an etch stop cavity; forming a layer of gate cap insulating material above said conformal etch stop layer in said etch stop cavity; and performing one or more CMP processes or one or more etch back process to remove portions of said conformal etch stop layer and said layer of gate cap insulating material so as to thereby define a gate cap structure comprising said conformal etch stop layer of gate cap insulating material positioned above said recessed sidewall spacers and said recessed final gate structure.
2. The method of claim 1 , wherein an upper surface of said recessed sidewall spacers define, in part, a spacer cavity having a first depth relative to an upper surface of a first layer of insulating material positioned adjacent said sidewall spacers.
3. The method of claim 2 , wherein an upper surface of said recessed final gate structure defines, at least in part, a recessed final gate structure cavity having a second depth relative to said upper surface of said first layer of insulating material that is greater than said first depth.
4. The method of claim 1 , wherein forming said etch stop layer comprises forming said etch stop layer from one of Al 2 O 3 or a high-k insulating material.
5. The method of claim 1 , wherein said sidewall spacers are comprised of silicon nitride and said etch stop layer is comprised of a high-k insulating material.
6. The method of claim 2 , further comprising: forming a second layer of insulating material above said first layers of insulating material and above said gate cap structure; forming a contact opening in at least said first and second layers of insulating material that exposes a contact region of said transistor; and forming a conductive contact structure in said contact opening that is conductively coupled to said contact region.
7. The method of claim 6 , wherein, prior to forming said conductive contact structure, the method further comprises: performing a conformal deposition process to form a dielectric liner layer at least in said contact opening and against at least a portion of said recessed sidewall spacers; and performing an isotropic etching process to remove at least portions of said dielectric liner layer.
8. The method of claim 7 , wherein said dielectric liner layer is one of silicon dioxide or a low-k oxide.
9. The method of claim 6 , wherein said contact region is a source/drain region.
10. The method of claim 1 , wherein said transistor is one of a planar FET or a FinFET.
11. The method of claim 1 , wherein a portion of said conformal etch stop layer has a stepped profile when viewed in cross-section.
12. A method, comprising: forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers positioned in a first layer of insulating material; removing a portion of said sidewall spacers to define recessed sidewall spacers and a spacer cavity having a first depth relative to an upper surface of said first layer of insulating material; removing a portion of said final gate structure to define a recessed final gate structure cavity having a second depth relative to said upper surface of said first layer of insulating material that is greater than said first depth; and performing a conformal deposition process to form a conformal etch stop layer on at least said recessed sidewall spacers, said recessed final gate structure, and said first layer of insulating material, said conformal etch stop layer having a stepped profile when viewed in cross-section, wherein said conformal etch stop layer defines an etch stop cavity; forming a layer of gate cap insulating material above said conformal etch stop layer in said etch stop cavity; and performing one or more CMP processes or one or more etch back processes to remove portions of said conformal etch stop layer and said layer of gate cap insulating material so as to thereby define a gate cap structure comprising said conformal etch stop layer and said layer of gate cap insulating material positioned above said recessed sidewall spacers and said recessed final gate structure.
13. The method of claim 12 , wherein said sidewall spacers are comprised of silicon nitride, said first layer of insulating material is comprised of silicon dioxide and said etch stop layer is comprised of high-k insulating material.
14. The method of claim 12 , further comprising: forming a second layer of insulating material above said first layers of insulating material; forming a contact opening in at least said first and second layers of insulating material that exposes a contact region of said transistor; and forming a conductive contact structure in said contact opening that is conductively coupled to said contact region.
15. The method of claim 14 , wherein, prior to forming said conductive contact structure, the method further comprises: performing a conformal deposition process to form a dielectric liner layer at least in said contact opening and against at least a portion of said recessed sidewall spacers; and performing an isotropic etching process to remove at least portions of said dielectric liner layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 17, 2013
January 6, 2015
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.