One embodiment sets forth a timing calibration technique for on-chip source-synchronous, complementary metal-oxide-semiconductor (CMOS) repeater-based interconnect. Two transition patterns may be applied to calibrate the delay of an on-chip data or clock wire. Calibration logic is configured to apply the transition patterns and then trim the delays of the clock and data wires based on captured calibration patterns. The trimming adjusts the delay of the clock and data wires using a configurable delay circuit. Timing errors may be caused by crosstalk, power-supply-induced jitter (PSIJ), or wire delay variation due to transistor and wire metallization mismatch. Chip yields may be improved by reducing the occurrence of timing errors due to mismatched delays between different wires of an on-chip interconnect.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for calibrating an on-chip interconnect, comprising: applying a first signal transition pattern that is a first binary pattern to a first wire of the on-chip interconnect that is coupled between a first transmitter and a first receiver to generate a plurality of first measurements that correspond to a timing characteristic of the first wire; and configuring, based on the plurality of first measurements, a delay circuit to adjust a delay of the first wire to fall within a range of a predetermined delay variation that is substantially centered on an edge of a clock signal.
2. The method of claim 1 , further comprising applying a second signal transition pattern that is a second binary pattern to the first wire of the on-chip interconnect to generate a plurality of second measurements that correspond to the timing characteristic of the first wire, wherein the delay circuit is further configured, based on the plurality of second measurements, to adjust the delay of the first wire to fall within the range of the predetermined delay variation.
3. The method of claim 1 , further comprising: determining a delay distribution associated with the first wire and other wires of the on-chip interconnect; and positioning the edge of the clock signal to substantially center the edge of the dock signal within the delay distribution.
4. The method of claim 1 , wherein the plurality of first measurements indicates that a delay associated with the first wire is negative relative to the edge of the clock signal, and wherein the delay circuit is configured to increase the delay associated with the first wire.
5. The method of claim 1 , wherein the plurality of first measurements indicates that a delay associated with the first wire is positive relative to the edge of the clock signal, and wherein the delay circuit is configured to decrease the delay associated with the first wire.
6. The method of claim 1 , wherein the delay circuit is configured to increase or decrease a delay associated with the first wire by an amount equal to the range of the predetermined delay variation.
7. The method of claim 1 , wherein the delay circuit is configured to increase or decrease a delay associated with the first wire by an amount equal to an integer multiple of the range of the predetermined delay variation.
8. The method of claim 1 , wherein the range of the predetermined delay variation is associated with a target yield of a chip comprising the on-chip interconnect.
9. The method of claim 1 , further comprising, after configuring, adjusting the clock signal to substantially center the edge of the clock signal between transitions of a signal transmitted on the first wire.
10. The method of claim 1 , further comprising transmitting data on the first wire of the on-chip interconnect, and transmitting the clock signal on a second wire of the on-chip interconnect that is coupled between a second transmitter and a second receiver.
11. The method of claim 1 , wherein the delay circuit is configured to delay rising edges of a data signal transmitted on the first wire by a first amount and delay falling edges of the data signal by a second amount.
12. The method of claim 1 , further comprising configuring a second delay circuit to delay rising edges of the clock signal by a first amount and delay falling edges of the clock signal by a second amount.
13. An on-chip interconnect calibration system, comprising: a calibration pattern generation unit configured to generate a first signal transition pattern that is a first binary pattern; a calibration pattern capture unit configured to generate a plurality of first measurements that correspond to a timing characteristic of a first wire of the on-chip interconnect that is coupled between a first transmitter and a first receiver; a delay circuit that is coupled to the first wire of the on-chip interconnect; and a calibration control unit that is coupled to the calibration pattern generation unit and a calibration pattern capture unit and configured to: apply the first signal transition pattern to the first wire of the on-chip interconnect to generate the plurality of first measurements; and configure, based on the plurality of first measurements, the delay circuit to adjust a delay of the first wire to fall within a range of a predetermined delay variation that is substantially centered on an edge of a clock signal.
14. The on-chip interconnect calibration system of claim 13 , wherein the calibration pattern generation unit is further configured to generate a second signal transition pattern that is a second binary pattern, the calibration pattern capture unit is further configured to generate a plurality of second measurements that correspond to the timing characteristic of the first wire, the calibration control unit is further configured to apply the second signal transition pattern to the first wire of the on-chip interconnect to generate the plurality of second measurements and, based on the plurality of second measurements, configure the delay circuit to adjust the delay of the first wire to fall within the range of the predetermined delay variation.
15. The on-chip interconnect calibration system of claim 13 , further comprising a clock switch unit that is coupled to the calibration control unit and configured to generate the clock signal.
16. The on-chip interconnect calibration system of claim 13 , further comprising a second delay unit that is coupled to a second wire that transmits the clock signal and is coupled between a second transmitter and a second receiver, wherein the calibration control unit configures the second delay unit to substantially center the edge of the clock signal within a delay distribution associated with the first wire and other wires of the on-chip interconnect.
17. The on-chip interconnect calibration system of claim 13 , wherein the plurality of first measurements indicates that a delay of the first wire is negative relative to the edge of the clock signal and the delay circuit is configured by the calibration control unit to increase the delay associated with the first wire.
18. The on-chip interconnect calibration system of claim 13 , wherein the plurality of first measurements indicates that a delay of the first wire is positive relative to the edge of the clock signal and the delay circuit is configured by the calibration control unit to decrease the delay associated with the first wire.
19. The on-chip interconnect calibration system of claim 13 , wherein the delay circuit is configured by the calibration control unit to increase or decrease a delay associated with the first wire by an amount equal to the range of the predetermined delay variation.
20. The on-chip interconnect calibration system of claim 13 , wherein the range of the predetermined delay variation is associated with a target yield of a chip comprising the on-chip interconnect.
21. The on-chip interconnect calibration system of claim 13 , further comprising a second delay unit that is coupled to a second wire between a second transmitter and a second receiver that transmits the clock signal, the second delay unit, further configured by the calibration control unit to adjust the clock signal to substantially center the edge of the clock signal between transitions of a data signal transmitted on the first wire.
22. A computing system, comprising: an on-chip interconnect calibration system, comprising: a calibration pattern generation unit configured to generate a first signal transition pattern that is a first binary pattern; a calibration pattern capture unit configured to generate a plurality of first measurements that correspond to a timing characteristic of a first wire of the on-chip interconnect that is coupled between a first transmitter and a first receiver; a delay circuit that is coupled to the first wire of the on-chip interconnect; and a calibration control unit that is coupled to the calibration pattern generation unit and the calibration pattern capture unit and configured to: apply the first signal transition pattern to the first wire of the on-chip interconnect to generate the plurality of first measurements; and configure, based on the plurality of first measurements, the delay circuit to adjust a delay of the first wire to fall within a range of a predetermined delay variation that is substantially centered on an edge of a clock signal.
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September 12, 2012
January 27, 2015
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