In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating a semiconductor device, comprising: forming an opening inside a dielectric layer over a substrate, the opening having a wall; forming at least one diffusion barrier material comprising a metal nitride over the wall of the opening by at least two alternating steps selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD), the at least one diffusion barrier layer comprises: at least one layer comprising tantalum nitride (TaN), wherein the atomic ratio of tantalum (Ta) to nitrogen (N) is substantially 1:1, and at least a second layer comprising TaNx, wherein x is a number in the range of from 0.5 to 1.5; and forming a liner layer over the at least one diffusion barrier material.
2. The method of claim 1 , wherein the step of forming the at least one the diffusion barrier material comprises: depositing the at least one diffusion barrier material using a PVD process; and then depositing the at least one diffusion barrier material using an ALD process.
3. The method of claim 1 , wherein the step of forming the at least one diffusion barrier material comprises: depositing the at least one diffusion barrier material using an ALD process; and then depositing the at least one diffusion barrier material using a PVD process.
4. The method of claim 1 , wherein the step of forming the at least one diffusion barrier material comprises, in the following sequence: depositing the at least one diffusion barrier material using an ALD process; depositing the at least one diffusion barrier material using a PVD process; and depositing the at least one diffusion barrier material using an ALD process.
5. The method of claim 1 , wherein the at least one diffusion barrier material comprises tantalum nitride (TaN).
6. The method of claim 1 , wherein in each of the at least two alternating steps of depositing the at least one diffusion barrier material, the at least one diffusion barrier material is deposited in a thickness in the range of from about 5 angstroms to about 30 angstroms.
7. The method of claim 6 , wherein in each of the at least two alternating steps of depositing the at least one diffusion barrier material, the at least one diffusion barrier material is deposited in a thickness in the range of from about 10 angstroms to about 20 angstroms.
8. The method of claim 1 , further comprising: filling the opening with a conductive material by depositing the conductive material over the liner layer.
9. The method of claim 8 , wherein the liner layer comprises one or more metal elements selected from ruthenium (Ru), rhodium (Rh), hafnium (Hf), iridium (Ir), niobium (Nb), molybdenum (Mo), rhenium (Re), ruthenium (Ru), osmium (Os), tungsten (W), cobalt (Co), titanium (Ti), manganese (Mn), palladium (Pd), platinum (Pt), or silver (Ag).
10. The method of claim 8 , wherein the conductive material comprises copper (Cu), aluminum (Al), silver (Ag), gold (Au), tungsten (W), or alloys thereof.
11. The method of claim 1 , wherein x is in the range of from 1 to 1.5.
12. A method of fabricating a semiconductor device, comprising: forming an opening inside a dielectric layer over a semiconductor substrate, the opening having a wall; forming at least one diffusion barrier material over the wall of the opening, wherein the step of forming the at least one diffusion barrier material comprises, in the following sequence: depositing the at least one diffusion barrier material using an ALD process; depositing the at least one diffusion barrier material using a PVD process; and depositing the at least one diffusion barrier material using an ALD process; forming a liner layer over the at least one diffusion barrier material; and filling the opening with a conductive material by depositing the conductive material over the liner layer.
13. The method of claim 12 , wherein in each of the at least two alternating steps of depositing the at least one diffusion barrier material, the at least one diffusion barrier material is deposited in a thickness in the range of from 10 angstroms to 20 angstroms.
14. The method of claim 12 , wherein the at least one diffusion barrier material comprises tantalum nitride (TaN).
15. The method of claim 12 , wherein the liner layer comprises ruthenium (Ru), and the conductive material comprises copper (Cu).
16. The method of claim 12 , wherein the diffusion barrier layer comprises: at least one layer comprising tantalum nitride (TaN), wherein the atomic ratio of tantalum (Ta) to nitrogen (N) is substantially 1:1, and at least a second layer comprising TaNx, wherein x is a number in the range of from 0.5 to 1.5.
17. The method of claim 16 , wherein x is in the range of from 1 to 1.5.
18. A method of fabricating a semiconductor device, comprising: forming an opening inside a dielectric layer over a substrate, the opening having a wall; forming at least one diffusion barrier material over the wall of the opening, wherein the step of forming the at least one diffusion barrier material comprises, in the following sequence: depositing the at least one diffusion barrier material using an ALD process; depositing the at least one diffusion barrier material using a PVD process; and depositing the at least one diffusion barrier material using an ALD process; and forming a liner layer comprising ruthenium (Ru) over the at least one diffusion barrier material.
19. The method of claim 18 , further comprising: filling the opening with a conductive material comprising copper by depositing the conductive material over the liner layer.
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March 15, 2013
February 24, 2015
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