A pattern for use in the manufacture of semiconductor devices is provided which, according to an example embodiment, may comprise at least one second field region comprising a main array of dies, each having a height of Y1 and a width of X1, and the main array having a height of Y3. The pattern according to the example embodiment may further include at least one first field region comprising a monitoring region having a height of Y2 and a width of X2 and an auxiliary die region having a height of Y2 and comprising an auxiliary array of dies. The dimensions of the various regions may be proportional to one another, such that X2=n1×X1+adjustment1, Y2=n3×Y1+adjustment3, and Y3=n4×Y2+adjustment4, n1, n3, and n4 being integers.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor device of claim 1 , wherein Q is a proper divisor of Y 2 .
3. The semiconductor device of claim 1 , wherein Q=Y 2 .
4. The semiconductor device of claim 1 , wherein Y 2 and Y 3 are relatively prime.
5. The semiconductor device of claim 1 , wherein the first field region comprises a plurality of dies, the plurality of dies extending in at least one of the first direction or the second direction.
7. The semiconductor device of claim 1 , wherein the first field region further comprises a test chip region having a height of Y 2 and a width of X 3 , wherein X 3 =n 2 ×X 1 +adjustment 2 and n 2 is an integer.
8. The semiconductor device of claim 1 , further comprising n 4 −1 additional first field regions, the first field regions being arranged adjacent to one another along an axis corresponding to their respective heights so as to form an extended first field region, the extended first field region comprising an extended monitor region having a height of Y 3 and an extended auxiliary die region having a height of Y 3 .
9. The semiconductor device of claim 8 , wherein the extended first field region comprises a first extended first field region, the semiconductor device further comprising at least a second extended first field region, the first and second extended first field regions being arranged along an axis corresponding to their heights.
10. The semiconductor device of claim 9 , further comprising third, fourth, and fifth extended first field regions, the third extended first field region being arranged along the axis corresponding to the heights of the first and second extended first field regions, and the fourth and fifth extended first field regions being arranged on either side of the second extended first field region and along an axis corresponding to respective widths of the second, fourth, and fifth extended first field regions.
12. The photomask of claim 11 , wherein Q is a proper divisor of Y 2 .
13. The photomask of claim 11 , wherein Q=Y 2 .
14. The photomask of claim 11 , wherein Y 2 and Y 3 are relatively prime.
16. The photomask of claim 11 , wherein the first field region further comprises a test chip region having a height of Y 2 and a width of X 3 , wherein X 3 =n 2 ×X 1 +adjustment 2 and n 2 is an integer.
17. The photomask of claim 11 , wherein the photomask is further configured to cause projection of n 4 −1 additional first field regions, the first field regions being arranged adjacent to one another along an axis corresponding to their respective heights so as to form an extended first field region, the extended first field region comprising an extended monitor region having a height of Y 3 and an extended auxiliary die region having a height of Y 3 .
18. The photomask of claim 17 , wherein the extended first field region comprises a first extended first field region, the photomask being further configured to cause projection of at least a second extended first field region, the first and second extended first field regions being arranged along an axis corresponding to their heights.
19. The photomask of claim 18 , the photomask being further configured to cause projection of at least third, fourth, and fifth extended first field regions, the third extended first field region being arranged along the axis corresponding to the heights of the first and second extended first field regions, and the fourth and fifth extended first field regions being arranged on either side of the second extended first field region and along an axis corresponding to respective widths of the second, fourth, and fifth extended first field regions.
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May 3, 2013
March 3, 2015
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