A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A high voltage semiconductor transistor, comprising: a lightly doped semiconductor substrate having a first type of conductivity; a buried layer in a first portion of the semiconductor substrate having a second type of conductivity; a first well region having the second type of conductivity and formed over the lightly doped semiconductor substrate, the first well region having a lower dopant concentration than the buried layer, the buried layer being partially in the first well region; a second well region in the first well region and having the first type of conductivity, the second well region having a U-shape in a cross section between a drain and source, wherein both ends of the U-shape extends to a top surface of the first well region, and the cross section is taken in a direction perpendicular to a top surface of the lightly doped semiconductor substrate; a first insulating structure over and partially embedded in the first well region within the U-shape of the second well region and not contacting the second well region; a second insulating structure over a first end of the U-shape of the second well region; a gate structure near the first insulating structure over the first well region and partially over a second end of the U-shape of the second well region; a drain region in the first well region across the first insulating structure from the gate structure, the drain region comprising a first drain portion between the first insulating structure and the second insulating structure and a second drain portion across the second insulating structure from the first drain portion; an anti-punch through region below the first drain portion; and, a source region in the second well region disposed on a side of the gate structure opposite from the drain region.
2. The high voltage semiconductor transistor of claim 1 , further comprising another buried layer in a second portion of the semiconductor substrate having the second type of conductivity, wherein the another buried layer has a lower dopant concentration than the buried layer.
3. The high voltage semiconductor transistor of claim 1 , wherein each of the second well region, the first insulating structure, the second insulating structure, the gate structure, the drain region, and the source region has a conic section shape in a top view.
4. The high voltage semiconductor transistor of claim 3 , wherein the conic section is an ellipse.
5. The high voltage semiconductor transistor of claim 3 , wherein the conic section is a parabola.
6. The high voltage semiconductor transistor of claim 1 , wherein each of the semiconductor substrate, the buried layer, the first well region, the second well region, the first insulating structure, the second insulating structure, the gate structure, the drain region, and the source region includes a catenary shape in a top view.
7. The high voltage semiconductor transistor of claim 1 , wherein the second well region comprises a first portion, a second portion, and a third portion, the first portion and the third portion being ends of the U-shape and the second portion being a bottom of the U-shape, and wherein the first portion and the third portion are different sizes.
8. The high voltage semiconductor transistor of claim 7 , wherein each of the first portion, the second portion, and the third portion of the second well have different peak dopant concentrations.
9. The high voltage semiconductor transistor of claim 1 , wherein the anti-punch through region has the second type of conductivity with a higher peak dopant concentration than the first well region.
10. The high voltage semiconductor transistor of claim 1 , wherein the source region comprises a first source region having the first type of conductivity and a second source region having the second type of conductivity.
11. The high voltage semiconductor transistor of claim 1 , wherein the gate structure comprises a gate electrode, the gate electrode comprising a polysilicon.
12. The high voltage semiconductor transistor of claim 1 , wherein the gate structure comprises a gate dielectric, the gate dielectric comprising silicon oxide, or a high-K dielectric material.
13. The high voltage semiconductor transistor of claim 1 , the gate structure is formed partly on the first insulating structure.
14. The high voltage semiconductor transistor of claim 1 , wherein the first type of conductivity is p-type and the second type of conductivity is n-type.
15. A high voltage semiconductor transistor, comprising: a semiconductor substrate; a first well region, having a first type of conductivity, over the semiconductor substrate; a second well region in the first well region, the second well region having a second type of conductivity opposite the first type of conductivity, wherein the second well region comprises: a first portion extending parallel to a top surface of the first well region, a second portion extending from a first end of the first portion to the top surface of the first well region, and a third portion extending from a second end of the first portion, opposite the first end, to the top surface of the first well region, wherein the second well defines an enclosed portion of the first well region surrounded by the second well region; a first insulating structure over and partially embedded in the enclosed portion and separated from the second well region; a gate structure near the first insulating structure over the enclosed portion and partially over the first portion of the second well region; a drain region in the first well region across the first insulating structure from the gate structure, the drain region comprising a first drain portion in the enclosed portion and a second drain portion outside the enclosed portion; and a source region in the second well region disposed on a side of the gate structure opposite from the drain region.
16. The high voltage semiconductor transistor of claim 15 , further comprising: a first buried layer in the semiconductor substrate at a portion of an interface between the first well region and the semiconductor substrate, the first buried layer having a first dopant concentration; and a second buried layer in the semiconductor substrate and in the first well region, the second buried layer having a second dopant concentration different from the first dopant concentration.
17. The high voltage semiconductor transistor of claim 15 , further comprising a second insulating structure over the third portion of the second well region, wherein the second insulating structure is between the first drain portion and the second drain portion.
18. The high voltage semiconductor transistor of claim 15 , wherein a width of the first portion of the second well region in a direction parallel to the top surface of first well region is greater than a width of the third portion of the second well region in the direction parallel to the top surface of the first well region.
19. The high voltage semiconductor transistor of claim 15 , wherein each of the second well region, the first insulating structure, the gate structure, the drain region, and the source region has a conic section shape in a top view.
20. The high voltage semiconductor transistor of claim 15 , wherein each of the semiconductor substrate, the first well region, the second well region, the first insulating structure, the gate structure, the drain region, and the source region includes a catenary shape in a top view.
21. A high voltage semiconductor transistor, comprising: a lightly doped p-type semiconductor substrate; an n-type buried layer in a first portion of the semiconductor substrate; an n-type first well region over the semiconductor substrate, the first well region having a lower dopant concentration than the buried layer, wherein a portion of the buried layer is partially in the first well region; a p-type second well region in the first well region, the second well region having a U-shape in a cross section, wherein both ends of the U-shape extends to a top surface of the first well region and define an enclosed portion of the first well region, and the cross section is taken in a direction perpendicular to a top surface of the lightly doped semiconductor substrate; a first insulating structure partially embedded in the enclosed portion of the first well region; a second insulating structure over a first end of the U-shape of the second well region; a gate structure over the first well region and partially over a second end of the U-shape of the second well region, wherein the gate structure partially overlays the first insulating structure; a drain region in the first well region across the first insulating structure from the gate structure, the drain region comprising a first drain portion between the first insulating structure and the second insulating structure and a second drain portion across the second insulating structure from the first drain portion, wherein the second drain portion is over the portion of the buried layer partially in the first well region; an anti-punch through region below the first drain portion; and, a source region in the second well region disposed on a side of the gate structure opposite from the drain region.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 9, 2012
March 3, 2015
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