Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region and the drain region; a dielectric layer disposed over the substrate; and a gate contact, a source contact, and a drain contact. The dielectric layer is disposed over both etch stop layers. The gate contact extends through the dielectric layer and the first etch stop layer to the gate structure. The source contact and the drain contact extend through the dielectric layer and the second etch stop layer respectively to the source region and the drain region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a substrate; a gate structure disposed over the substrate; an etch stop layer disposed over the gate structure; a dielectric layer disposed over the etch stop layer; and a gate contact extending through the dielectric layer and the etch stop layer to the gate structure.
2. The semiconductor device of claim 1 , wherein the gate structure includes a high-k gate dielectric and a metal gate electrode, the gate contact being coupled to the metal gate electrode.
3. The semiconductor device of claim 1 , wherein the etch stop layer comprises silicon nitride.
4. The semiconductor device of claim 1 , further including a source region and a drain region disposed in the substrate.
5. The semiconductor device of claim 4 , further comprising a contact etch stop layer disposed over the source region and the drain region.
6. The semiconductor device of claim 5 , further comprising an interlayer dielectric (ILD) layer disposed between the dielectric layer and the contact etch stop layer.
7. The semiconductor device of claim 5 , wherein the dielectric layer is disposed over the contact etch stop layer.
8. A semiconductor device comprising: a substrate; at least one gate structure disposed over the substrate, a hard mask layer disposed over the at least one gate structure; a dielectric layer disposed over the hard mask layer; and one or more contacts, wherein at least one contact extends through the dielectric layer and the hard mask layer to the at least one gate structure.
9. The semiconductor device of claim 8 , wherein the at least one gate structure comprises a high-k gate dielectric and a metal gate electrode.
10. The semiconductor device of claim 9 , wherein the at least one contact extending through the dielectric layer and the hard mask layer is coupled to the metal gate electrode.
11. The semiconductor device of claim 8 , wherein the hard mask layer comprises silicon nitride.
12. The semiconductor device of claim 8 , further including a source region and a drain region disposed in the substrate, and the at least one gate structure interposes the source region and the drain region.
13. The semiconductor device of claim 12 , further comprising an etch stop layer disposed over the source region and the drain region.
14. The semiconductor device of claim 13 , further comprising an interlayer dielectric (ILD) layer disposed between the dielectric layer and the etch stop layer.
15. The semiconductor device of claim 13 , wherein the dielectric layer is disposed over the etch stop layer.
16. A semiconductor device comprising: a substrate having a source region and a drain region; a gate structure disposed over the substrate; a silicon nitride layer disposed over the gate structure; a dielectric layer disposed over the silicon nitride layer; and one or more contacts, wherein at least one contact extends through the dielectric layer and the silicon nitride layer to the at least one gate structure.
17. The semiconductor device of claim 16 , wherein the gate structure comprises a high-k gate dielectric and a metal gate electrode.
18. The semiconductor device of claim 16 , wherein the dielectric layer comprises an oxide material.
19. The semiconductor device of claim 16 , further comprising an etch stop layer disposed over the source region and the drain region.
20. The semiconductor device of claim 19 , further comprising an interlayer dielectric (ILD) layer disposed between the dielectric layer and the etch stop layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 20, 2013
March 3, 2015
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